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On the Excitability of Ultra-Low-Power CMOS Analog Spiking Neurons

Léopold Van Brandt, Grégoire Brandsteert, Denis Flandre

TL;DR

The paper investigates the excitability of an ultra-low-power CMOS analog spiking neuron using SPICE-based simulations with industrial transistor models. It shows that a membrane-potential threshold $V_{ m m,th}$ is intrinsic to the neuron, while the critical charge $ riangle Q_{ m th}(I_{ m ex})$ required to spike depends on the input stimulus, making it non-intrinsic. By introducing an effective nonlinear membrane capacitance $C_{ m m,eff}(t)$, the authors relate the threshold charge to the voltage threshold via $ riangle Q_{ m th} = ar{C}_{ m m,eff} riangle V_{ m m,th}$ and analyze the neuron’s dynamics in a 2D state space $(v_{ m m}, v_{ m GNA})$, including a separatrix that governs spike initiation and an always-spiking limit cycle under sustained drive. The work demonstrates how a biologically-inspired integrate-and-fire-like response emerges in a compact, low-power circuit and lays the groundwork for future studies on noise and jitter in neuromorphic hardware.

Abstract

The excitability property of spiking neurons describes their capability to output an action potential as a real-time response to an input synaptic excitation current and is central to the event-based neuromorphic computing paradigm. The spiking mechanism is analysed in a representative ultra-low-power analog neuron from the circuit literature. Relying on conventional SPICE simulations compatible with industrial transistor compact models, we establish a excitation criterion, quantified either in terms of critical supplied charge or membrane potential threshold. Only the latter is found intrinsic to the neuron, i.e. independent of the input stimulus. Rigorous analysis of the nonlinear neuron dynamics provides insight but still needs to be explored further, as well as the effect of the intrinsic noise.

On the Excitability of Ultra-Low-Power CMOS Analog Spiking Neurons

TL;DR

The paper investigates the excitability of an ultra-low-power CMOS analog spiking neuron using SPICE-based simulations with industrial transistor models. It shows that a membrane-potential threshold is intrinsic to the neuron, while the critical charge required to spike depends on the input stimulus, making it non-intrinsic. By introducing an effective nonlinear membrane capacitance , the authors relate the threshold charge to the voltage threshold via and analyze the neuron’s dynamics in a 2D state space , including a separatrix that governs spike initiation and an always-spiking limit cycle under sustained drive. The work demonstrates how a biologically-inspired integrate-and-fire-like response emerges in a compact, low-power circuit and lays the groundwork for future studies on noise and jitter in neuromorphic hardware.

Abstract

The excitability property of spiking neurons describes their capability to output an action potential as a real-time response to an input synaptic excitation current and is central to the event-based neuromorphic computing paradigm. The spiking mechanism is analysed in a representative ultra-low-power analog neuron from the circuit literature. Relying on conventional SPICE simulations compatible with industrial transistor compact models, we establish a excitation criterion, quantified either in terms of critical supplied charge or membrane potential threshold. Only the latter is found intrinsic to the neuron, i.e. independent of the input stimulus. Rigorous analysis of the nonlinear neuron dynamics provides insight but still needs to be explored further, as well as the effect of the intrinsic noise.

Paper Structure

This paper contains 9 sections, 5 equations, 5 figures, 1 table.

Figures (5)

  • Figure 1: \ref{['fig_neuron']} Diagram of a CMOS analog spiking neuron Sourikopoulos2017. \ref{['fig_waveforms']} Waveforms at the different nodes of the circuit labelled in \ref{['fig_neuron']} under constant excitation current pulse of amplitude $I_{\mathrm{ex}} = 40pA$. Resting membrane potential is $V_{\mathrm{m,res}} \approx 22mV$ and threshold potential $V_{\mathrm{m,res}} \approx 64mV$. Case study: $65nm$ CMOS technology design of Sourikopoulos2017, whose parameters are given in \ref{['tab:param']} and operating at ultra low $V_{\mathrm{DD}} = 200mV$ and $T = 300K$.
  • Figure 2: \ref{['fig_excitability']} Threshold property of the excitable neuron of \ref{['fig_neuron']} (plot suggested by Sepulchre2018Sepulchre2025), extracted from deterministic SPICE transient simulations with a sweep on excitation current pulse parameters $(I_{\mathrm{ex}},\Delta T_{\mathrm{p}})$, resp. amplitude and duration. The green region corresponds to input pulses $i_{\mathrm{ex}}$ that lead to an action potential, i.e. a spike on output $v_{\mathrm{GK}}$. Low-energy pulses located in the red region fail to active the spiking mechanism of the circuit. \ref{['fig_waveforms_Iex_10pA_pw_80us']}\ref{['fig_waveforms_Iex_15pA_pw_20us']} Membrane and action potential waveforms of two illustrative cases marked by dots in \ref{['fig_excitability']}, in addition to the case shown in \ref{['fig_waveforms']}. For the pulse \ref{['fig_waveforms_Iex_10pA_pw_80us']}, the membrane potential crosses the threshold $V_{\mathrm{m,th}}$ and the neuron fires a spike. The pulse \ref{['fig_waveforms_Iex_15pA_pw_20us']} does not supply a sufficient amount of energy.
  • Figure 3: Definition of the threshold potential $V_{\mathrm{m,th}}$ as the value reached by $v_{\mathrm{m}}$ when excited by a current pulse of duration $\Delta T_{\mathrm{p,th}}(I_{\mathrm{ex}})$ provided by \ref{['fig_excitability']} for some given amplitude $I_{\mathrm{ex}}$. While $I_{\mathrm{ex}} = 40pA$ was arbitrarily chosen for illustration (as in \ref{['fig_waveforms']}), the threshold $V_{\mathrm{m,th}}$ is an intrinsic property of the neuron and does not depend on $I_{\mathrm{ex}}$. The extraction of the nonlinear effective total membrane capacitance $C_{\mathrm{m,eff}}$ according to the definition \ref{['eq:CMtot']} is also shown; $\overline{C}_{\mathrm{m,eff}}$ denotes the averaged effective capacitance over the phase 1 during which $v_{\mathrm{m}}$ rises from $V_{\mathrm{m,res}}$ to $V_{\mathrm{m,th}}$.
  • Figure 4: Trajectory in the 2D state subspace $(v_{\mathrm{m}},v_{\mathrm{GNA}})$, corresponding to the simulated waveforms and operation phases of \ref{['fig_waveforms']}. Membrane potential $V_{\mathrm{m,res}}$ and the threshold potential $V_{\mathrm{m,res}}$ are indicated. The quasi-static voltage transfer characteristics $V_{\mathrm{GNA}} = f_{1}(V_{\mathrm{m}})$ (inverter MN1-MP1) and $V_{\mathrm{m}} = f_{\mathrm{NA}}(V_{\mathrm{GNA}})$ (transistor MPNa with a feedback effect of the whole circuit) are shown in brown lines, resp. full and dashed.
  • Figure 5: Action potential train (output spike train) sustained by \ref{['fig_waveforms_long_pulse']} a constant synaptic excitation current pulse; \ref{['fig_waveforms_spike_train']} a synaptic current spike train. Illustrated case: same neuron design as \ref{['fig_neuron_waveforms']} and \ref{['tab:param']}.