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LILogic Net: Compact Logic Gate Networks with Learnable Connectivity for Efficient Hardware Deployment

Katarzyna Fojcik, Renaldas Zioma, Jogundas Armaitis

TL;DR

LILogic Net introduces learnable connectomes for differentiable logic gate networks to achieve high accuracy with far fewer binary gates, enabling efficient hardware deployment. By jointly training gate behavior and interconnections and employing a projection-based gate evaluation, the approach yields fast convergence and strong performance on MNIST (98.45% with 8K gates) and CIFAR-10 (60.98% with 256K gates). The method supports multiple interconnect strategies, including Top-$K$ sparsity, and demonstrates favorable accuracy–efficiency trade-offs across architectures, datasets, and hardware budgets. This work expands the Pareto frontier for logic-gate-based models, highlighting practical pathways to deploy hardware-native AI on low-power devices while maintaining competitive performance.

Abstract

Efficient deployment of machine learning models ultimately requires taking hardware constraints into account. The binary logic gate is the fundamental building block of all digital chips. Designing models that operate directly on these units enables energy-efficient computation. Recent work has demonstrated the feasibility of training randomly connected networks of binary logic gates (such as OR and NAND) using gradient-based methods. We extend this approach by using gradient descent not only to select the logic gates but also to optimize their interconnections (the connectome). Optimizing the connections allows us to substantially reduce the number of logic gates required to fit a particular dataset. Our implementation is efficient both at training and inference: for instance, our LILogicNet model with only 8,000 gates can be trained on MNIST in under 5 minutes and achieves 98.45% test accuracy, matching the performance of state-of-the-art models that require at least two orders of magnitude more gates. Moreover, for our largest architecture with 256,000 gates, LILogicNet achieves 60.98% test accuracy on CIFAR-10 exceeding the performance of prior logic-gate-based models with a comparable gate budget. At inference time, the fully binarized model operates with minimal compute overhead, making it exceptionally efficient and well suited for deployment on low-power digital hardware.

LILogic Net: Compact Logic Gate Networks with Learnable Connectivity for Efficient Hardware Deployment

TL;DR

LILogic Net introduces learnable connectomes for differentiable logic gate networks to achieve high accuracy with far fewer binary gates, enabling efficient hardware deployment. By jointly training gate behavior and interconnections and employing a projection-based gate evaluation, the approach yields fast convergence and strong performance on MNIST (98.45% with 8K gates) and CIFAR-10 (60.98% with 256K gates). The method supports multiple interconnect strategies, including Top- sparsity, and demonstrates favorable accuracy–efficiency trade-offs across architectures, datasets, and hardware budgets. This work expands the Pareto frontier for logic-gate-based models, highlighting practical pathways to deploy hardware-native AI on low-power devices while maintaining competitive performance.

Abstract

Efficient deployment of machine learning models ultimately requires taking hardware constraints into account. The binary logic gate is the fundamental building block of all digital chips. Designing models that operate directly on these units enables energy-efficient computation. Recent work has demonstrated the feasibility of training randomly connected networks of binary logic gates (such as OR and NAND) using gradient-based methods. We extend this approach by using gradient descent not only to select the logic gates but also to optimize their interconnections (the connectome). Optimizing the connections allows us to substantially reduce the number of logic gates required to fit a particular dataset. Our implementation is efficient both at training and inference: for instance, our LILogicNet model with only 8,000 gates can be trained on MNIST in under 5 minutes and achieves 98.45% test accuracy, matching the performance of state-of-the-art models that require at least two orders of magnitude more gates. Moreover, for our largest architecture with 256,000 gates, LILogicNet achieves 60.98% test accuracy on CIFAR-10 exceeding the performance of prior logic-gate-based models with a comparable gate budget. At inference time, the fully binarized model operates with minimal compute overhead, making it exceptionally efficient and well suited for deployment on low-power digital hardware.

Paper Structure

This paper contains 24 sections, 4 equations, 6 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. Method
  4. Differentiable Logical Gate Networks
  5. Model Architecture
  6. Dataset and Preprocessing
  7. Training and Inference
  8. Timing measurements
  9. Differentiable Relaxation
  10. Learnable Interconnections
  11. Binarization
  12. Classification Strategy
  13. Experiments
  14. Training Time Comparison: Full Gate Evaluation vs. Basis Projection
  15. Interconnect Strategy Analysis
  16. ...and 9 more sections

Figures (6)

  • Figure 1: Gate count vs. accuracy on the MNIST dataset. Our models LILogic Nets achieve significantly higher accuracy for a given gate budget compared to state-of-the-art baselines, lying well above the Pareto front.
  • Figure 2: Overview of training-time interconnect strategies.
  • Figure 3: Inference pipeline: all logic gates and connections are fully binarized, yielding a compact, deterministic circuit.
  • Figure 4: Test accuracy vs. depth for various interconnects.
  • Figure 5: Convergence of 2K-width Top-$K$ test accuracy to $L$-type connectivity as $K$ increases.
  • ...and 1 more figures