Performance results of the first version of the MIZAR ASIC for the PBR mission

TL;DR

The paper presents the first version of the MIZAR ASIC, a 64-channel front-end designed to detect nanosecond-scale Cherenkov signals from EAS observed from sub-orbital and orbital platforms, addressing stringent timing and waveform requirements with a $64$-channel, $8\times8$ SiPM array architecture. It describes a sophisticated FE architecture with $256$ analog memory cells per channel, a $12$-bit Wilkinson ADC per cell, and $200\ \mathrm{MS/s}$ sampling, with derandomized, segmented memory and a digital-on-top layout feeding a $400$ MHz DDR serializer to an FPGA-based trigger system. Preliminary tests on six bonded chips show that the design meets power and readout targets, achieving around $5\ \mathrm{mW}$ per channel and full readout times on the order of $\sim 34.7\ \mu\mathrm{s}$, validating the feasibility for the POEMMA PBR mission. The results support further evaluation and pave the way for flight integration, with ongoing characterization and optimization expected in the near term.

Abstract

The Multi-channel Intergrated Zone-sampling Analogue-memory based Readout (MIZAR) ASIC is a new type of front-end electronics which has been developed for the detection of the optical Cherenkov signals by Extensive Air Showers directly observed from sub-orbital and orbital altitudes. It sets the stage for a new generation of low-power consuming 64-channel Application-Specific Integrated Circuit (ASIC). The ASIC is implemented in a commercial 65 nm CMOS technology to readout an 8$\times$8 matrix of Silicon Photo-Multipliers (SiPMs). The event is recorded at channel level in an array of 256 cells, each one equipped with an analogue memory, a 12-bits Wilkinson Analog-to-Digital Converter (ADC) and latches running at a sampling rate of 200 MS/s. The converted data are sent off-chip to a Field Programmable Gate Array (FPGA) which controls the digital end-of-column logic of the ASIC and implements the trigger logic. The goal is to employ it for the first time on the POEMMA Balloon with Radio (PBR) NASA mission which is devoted to measure Ultra-High Energy Cosmic Rays (UHECRs) and perform neutrino astronomy from stratospheric altitudes through the detection of atmospheric Cherenkov light. The first version of the MIZAR ASIC has been sent to production and it is now under test at INFN Torino. The results of the preliminary tests related to the characterization of the chip are presented.

Figures (5)

• Figure 1: Block diagram of the MIZAR architecture.
• Figure 2: Layout of a section made of 32 cells. In the round area a single cell is magnified next to the analog schematic.
• Figure 3: [Top] Hitmap validator pattern case: various patterns are searched by the FPGA to determine whether data is accepted or rejected. [Bottom] Pattern matching algorithm: each pixel is classified as main (M), and the pattern fingerprint is verified. This procedure is carried out in parallel for every pixel and each pattern case Bertaina:2023.
• Figure 4: A. Block diagram of testing setup. B. FEB and MIZAR bonded on the board
• Figure 5: Test pulse acquisition on channel 5, chip 1. 8 bit configuration, 32 cells partitioning.