Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity Testing

TL;DR

The paper tackles the bottleneck of slow, data-heavy linearity testing for high-resolution SAR ADCs. It introduces Uncertainty-Guided Live Measurement Sequencing (UGLMS), a closed-loop method that uses a residual-based Extended Kalman Filter to update capacitor-mismatch parameters in real time and selects measurement points by information gain, eliminating offline reconstruction. Experiments and simulations show sub-0.4 LSB INL/DNL accuracy with test times under tens of milliseconds and robust performance across resolutions and noise levels. The approach promises substantial production- test-time reductions and reduced data transfer, enabling efficient in-situ characterization of SAR ADCs.

Abstract

This paper introduces a novel closed-loop testing methodology for efficient linearity testing of high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). Existing test strategies, including histogram-based approaches, sine wave testing, and model-driven reconstruction, often rely on dense data acquisition followed by offline post-processing, which increases overall test time and complexity. To overcome these limitations, we propose an adaptive approach that utilizes an iterative behavioral model refined by an Extended Kalman Filter (EKF) in real time, enabling direct estimation of capacitor mismatch parameters that determine INL behavior. Our algorithm dynamically selects measurement points based on current model uncertainty, maximizing information gain with respect to parameter confidence and narrowing sampling intervals as estimation progresses. By providing immediate feedback and adaptive targeting, the proposed method eliminates the need for large-scale data collection and post-measurement analysis. Experimental results demonstrate substantial reductions in total test time and computational overhead, highlighting the method's suitability for integration in production environments.

Figures (8)

• Figure 1: Schematic of a SAR ADC including a capacitive DAC with binary-weighted structure. Core components such as the sample-and-hold input stage, DAC switch array, comparator, and control logic are shown.
• Figure 2: Example of a sweep used to estimate an ADC code edge under noise. The high-resolution DAC used for sampling here has $4$ bits more resolution than the ADC under test, enabling voltage steps of $1/16\,\mathrm{LSB}$. A total of 64 samples are uniformly distributed over a range of $\pm 0.25\,LSB$ around the predicted transition, resulting in 8 DAC input levels, each tested with 8 samples. Gray vertical lines indicate sampled input voltages, each with a vertical scale from 0 to 1 (in steps of $1/8$) showing how many samples hit code 42 or 43.
• Figure 3: INL and DNL of a 12-bit ADC reconstructed after 200 iterations using 64 samples per local sweep. Top: estimated and true INL/DNL. Bottom: absolute deviation. Measurement noise was set to $1.0\,\mathrm{LSB}$ RMS.
• Figure 4: Convergence of maximum INL and DNL estimation error over 1000 iterations for ADCs with different resolutions. Measurement noise was $1.0\,\mathrm{LSB}$ RMS; each measurement sweep used 64 samples.
• Figure 5: Convergence of maximum INL and DNL estimation error for different samples per measurement sweep. A 16-bit ADC in combination with $1.0\,LSB$ RMS noise was used.