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HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support

Zizheng Guo, Haichuan Liu, Xizhe Shi, Shenglu Hua, Zuodong Zhang, Chunyuan Zhao, Runsheng Wang, Yibo Lin

TL;DR

HeteroSTA tackles the need for fast, accurate static timing analysis in heterogeneous CPU-GPU EDA workflows by delivering a self-contained engine with robust industry-format support and a zero-overhead API. It combines two delay models (Elmore and Arnoldi) and full handling of timing exceptions, enabling end-to-end acceleration for graph- and path-based timing queries without relying on external tools. Experiments show strong correlation to PrimeTime and resilience to complex timing-exception scenarios, along with significant speedups in timing-driven placement and routing flows. The work enables practical, scalable integration of GPU-accelerated STA into production-style design flows, with future work targeting CCS and broader sign-off features.

Abstract

We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of delay calculation models providing versatile accuracy-speed choices without relying on an external golden tool, (2) robust support for industry formats, including especially the .sdc constraints containing all common timing exceptions, clock domains, and case analysis modes, and (3) end-to-end GPU-acceleration for both graph-based and path-based timing queries, all exposed as a zero-overhead flattened heterogeneous application programming interface (API). HeteroSTA is publicly available with both a standalone binary executable and an embeddable shared library targeting ubiquitous academic and industry applications. Example use cases as a standalone tool, a timing-driven DREAMPlace 4.0 integration, and a timing-driven global routing integration have all demonstrated remarkable runtime speed-up and comparable quality.

HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support

TL;DR

HeteroSTA tackles the need for fast, accurate static timing analysis in heterogeneous CPU-GPU EDA workflows by delivering a self-contained engine with robust industry-format support and a zero-overhead API. It combines two delay models (Elmore and Arnoldi) and full handling of timing exceptions, enabling end-to-end acceleration for graph- and path-based timing queries without relying on external tools. Experiments show strong correlation to PrimeTime and resilience to complex timing-exception scenarios, along with significant speedups in timing-driven placement and routing flows. The work enables practical, scalable integration of GPU-accelerated STA into production-style design flows, with future work targeting CCS and broader sign-off features.

Abstract

We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of delay calculation models providing versatile accuracy-speed choices without relying on an external golden tool, (2) robust support for industry formats, including especially the .sdc constraints containing all common timing exceptions, clock domains, and case analysis modes, and (3) end-to-end GPU-acceleration for both graph-based and path-based timing queries, all exposed as a zero-overhead flattened heterogeneous application programming interface (API). HeteroSTA is publicly available with both a standalone binary executable and an embeddable shared library targeting ubiquitous academic and industry applications. Example use cases as a standalone tool, a timing-driven DREAMPlace 4.0 integration, and a timing-driven global routing integration have all demonstrated remarkable runtime speed-up and comparable quality.

Paper Structure

This paper contains 9 sections, 3 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Challenges of a Heterogeneous STA Library
  3. HeteroSTA
  4. Experimental Results
  5. Delay Calculation Accuracy
  6. Timing Exception Correctness
  7. Case Study: Timing-Driven Global Placement
  8. Case Study: Timing-Driven Global Routing
  9. Conclusion

Figures (3)

  • Figure 1: HeteroSTA supports various input and output combinations featuring holistic industry file format support and a zero-cost abstraction interface. It delivers an order of magnitude STA speed-up for heterogeneous EDA applications.
  • Figure 2: STA is heavily used in design flows: a fast timer is critical in speeding up design iterations. Different stages may require customized STA inputs, outputs, and functions.
  • Figure 3: The modular design of HeteroSTA showing inputs, outputs, and data interactions between submodules.