Transition from MOS to Ideal Capacitor Behavior Triggered by Tunneling in the Inversion Population Regime

TL;DR

The paper tackles the analytic description of inversion-layer formation in MOS structures by solving the nonlinear Poisson equation, a long-standing problem that resisted closed-form solutions since $1955$. Using a recently derived analytical solution to an equivalent differential equation, the author obtains closed-form expressions for the potential $\phi(z)$, the inversion-layer width $z_i$, and the charge distribution $\rho(z)$ as functions of gate voltage $V_G$, distance from the interface, and impurity concentration $N_A$. A saturation regime is identified in which inversion-layer characteristics stabilize and quantum tunneling through an Esaki-like barrier dominates transport, driving interfacial charge accumulation and reshaping the charge distribution toward a quasi-two-dimensional profile. This quantum-aware analytical framework provides a foundation for modeling and designing next-generation MOS devices, including MOSFETs and tunneling FETs, with implications for gate control and energy efficiency across oxide thickness $t_{ox}$ and doping profiles.

Abstract

An analytical solution to the nonlinear Poisson equation governing the inversion layer in metal-oxide-semiconductor (MOS) structures has recently been obtained, resolving a fundamental challenge in semiconductor theory first identified in 1955. This breakthrough enables the derivation of explicit expressions for relevant physical quantities, such as the inversion-layer width, electric potential, and charge distribution, as functions of gate voltage $V_G$, distance from oxide-semiconductor interface and impurity concentration. These quantities exhibit rapid variation during early-stage inversion but saturate once the gate voltage exceeds the threshold voltage by a few tenths of a volt signaling a transition in the MOS response to $V_G$. The onset of tunneling through the Esaki barrier leads to increased charge accumulation near the interface, reshaping the charge distribution into a two-dimensional profile and shifting the potential drop from the semiconductor to the oxide layer. This reconfiguration resembles the behavior of an ideal parallel-plate capacitor, with charge confined at the interface and the voltage drop localized across the oxide. We analyze this mechanism in detail and demonstrate, through explicit calculations, that the tunneling current through the Esaki-like barrier formed during inversion becomes dominant, effectively superseding classical inversion behavior. These results offer a new analytical foundation for quantum-aware device modeling and inform the design of next-generation MOSFET and tunneling FET architectures.

Figures (6)

• Figure 1: The operating regimes of the MOS seen through the behavior of the surface potential $\phi_s$ and the potential drop $\Delta \phi_{ox}$ in the oxide layer, as functions of the gate potential $V_G$. For this plot, we assume a $p$-type silicon semiconductor and a silicon-oxide layer 2nm thickness.
• Figure 2: The inversion layer width as function of the surface potential $\phi_s$. For these plots we consider $p$-type silicon semiconductors with the indicated doping concentrations and a 2nm-thick silicon-oxide layer.
• Figure 3: The charge concentration $\rho(z)$ as a function of $z$ for three different values of the surface potential. Increasing the gate potential, the charge density varies from almost a constant distribution towards a 2DEG distribution. In panel (b) the same figure but in logarithmic scale on the x-axis.
• Figure 4: Electric potential energy as a function of $z$, for different values of surface potential $\phi_s$, impurity concentration $N_A=10^{24}$/cm$^3$ and threshold potential $V_{Gu}$. The open circles indicate the inversion-layer width $z_i$. For the surface potentials, whose graphs are plotted here, the corresponding gate potentials are 1.45 V, 1.64 V, 3.05 V and $\sim$ 25700 V, respectively. The inset shows the potential energy in the inversion layer in both normal and logarithmic scales on the x-axis.
• Figure 5: Esaki barriers and tunneling current. In (a) electrons of the valence band capable of tunneling through the Esaki barriers whose widths diminish as the gate potential grows. In (b) the tunneling current calculated assuming a triangular shape for the Esaki barrier and an average width of 30nm.