Beamspace Equalization for mmWave Massive MIMO: Algorithms and VLSI Implementations

TL;DR

The paper tackles the high power and hardware cost of all-digital mmWave massive MU-MIMO by leveraging beamspace sparsity for data detection. It introduces CSPADE, an improved complex SPADE variant, and develops parallel adder-tree and MAC-based VLSI architectures with mute-capable multipliers to realize power-efficient beamspace equalization. Fixed-point simulations and post-layout 22nm FDSOI results show CSPADE can reduce power by up to 66% and achieve the highest throughput while maintaining competitive BER and energy/area efficiency relative to antenna-domain detectors and existing beamspace methods. The findings demonstrate that beamspace processing with CSPADE offers a practical and scalable path toward energy-efficient baseband processing in mmWave massive MIMO systems. The work provides concrete hardware designs, quantization guidelines, and a rigorous hardware-performance comparison against the state of the art.

Abstract

Massive multiuser multiple-input multiple-output (MIMO) and millimeter-wave (mmWave) communication are key physical layer technologies in future wireless systems. Their deployment, however, is expected to incur excessive baseband processing hardware cost and power consumption. Beamspace processing leverages the channel sparsity at mmWave frequencies to reduce baseband processing complexity. In this paper, we review existing beamspace data detection algorithms and propose new algorithms as well as corresponding VLSI architectures that reduce data detection power. We present VLSI implementation results for the proposed architectures in a 22nm FDSOI process. Our results demonstrate that a fully-parallelized implementation of the proposed complex sparsity-adaptive equalizer (CSPADE) achieves up to 54% power savings compared to antenna-domain equalization. Furthermore, our fully-parallelized designs achieve the highest reported throughput among existing massive MIMO data detectors, while achieving better energy and area efficiency. We also present a sequential multiply-accumulate (MAC)-based architecture for CSPADE, which enables even higher power savings, i.e., up to 66%, compared to a MAC-based antenna-domain equalizer.

Figures (11)

• Figure 1: Overview of the considered all-digital massive MU-MIMO uplink system. The spatial beamspace FFT exists only in beamspace architectures.
• Figure 2: Empirical PDF of real part of entries of (a) $\bar{\mathbf{W}\xspace}$/${\mathbf{W}\xspace}$ and (b) $\bar{\mathbf{y}\xspace}$/${\mathbf{y}\xspace}$ using LoS channels generated by QuaDRiGa. BD stands for beamspace domain and AD for antenna domain.
• Figure 3: Multiplier activity rate (equivalently, the density coefficient for EOMP and COMP) vs. SNR operating point at $0.1\%$ uncoded BER. In (a) and (b), the circled data points correspond to the parameters used in the VLSI implementations of each algorithm.
• Figure 4: Uncoded BER vs SNR for $64\times 8$ and $64 \times 16$ ($B\times U$) systems in LoS and non-LoS channels. The black curve shows the reference BER of floating-point ALMMSE equalization with unquantized inputs, while all other curves show the BER results with inputs quantized with $6$-bit ADCs. Furthermore, all curves except for the ALMMSE (unquantized & float) and LMMSE-SB equalizers, show the uncoded BER considering fixed-point computations.
• Figure 5: Architecture of (a) adder-tree (AT)-based equalizer for ALMMSE and EOMP and (b) mute-capable complex multiplier (MCM).

Theorems & Definitions (1)

• Remark 1