Quantum Design Automation: Foundations, Challenges, and the Road Ahead

TL;DR

This paper surveys Quantum Design Automation (QDA) as a holistic framework that unifies physical-level hardware design with logic-level quantum software for superconducting qubits. It details a two-domain workflow—physical design (chip layout, EM and electrostatics, Hamiltonian derivation, packaging, cryogenics, TCAD, and verification) and logic design (quantum ISA, circuit synthesis, optimization, and quantum error correction)—and explains how co-design principles enable end-to-end optimization. It highlights current tooling, methodologies, and bottlenecks across chip-level and circuit-level disciplines, and discusses forward-looking directions such as surrogate EM models, AI-assisted inverse design, dynamic circuits, fault-tolerant architectures, and integration with classical EDA techniques. The paper argues that bridging physical and logical design is essential to scale quantum hardware and translate research into practical quantum advantage, with implications for simulation, verification, and fault-tolerant quantum computing. It emphasizes the need for co-design frameworks, scalable verification, and hardware-aware compilation to realize robust, scalable quantum processors.

Abstract

Quantum computing is transitioning from laboratory research to industrial deployment, yet significant challenges persist: system scalability and performance, fabrication yields, and the advancement of algorithms and applications. We emphasize that in building quantum computers -- spanning quantum chips, system integration, instruction sets, algorithms, and middleware such as quantum error correction schemes -- design is everywhere. In this paper, we advocate for a holistic design perspective in quantum computing, a perspective we argue is pivotal to unlocking innovative co-design opportunities and addressing the aforementioned key challenges. To equip readers with sufficient background for exploring co-optimization opportunities, we detail how interconnected computational methods and tools collaborate to enable end-to-end quantum computer design. This coverage encompasses critical stages -- such as chip layout design automation, high-fidelity system-level simulation, Hamiltonian derivation for quantum system modeling, control pulse simulation, decoherence analysis, and physical verification and testing -- followed by quantum instruction set design. We then proceed to quantum system and software development, including quantum circuit synthesis, quantum error correction and fault tolerance, and logic verification and testing. Through these discussions, we illustrate with concrete examples -- including co-optimizing quantum instruction sets with algorithmic considerations, customizing error correction circuits to hardware-specific constraints, and streamlining quantum chip design through tailored code design, among others. We hope that the detailed end-to-end design workflow as well as these examples will foster dialogue between the hardware and software communities, ultimately facilitating the translation of meaningful research findings into future quantum hardware implementations.

Figures (8)

• Figure 1: The comprehensive illustration of the QDA workflow, which describe the co-design process connecting the physical-level and the logic-level design stages. The proposed workflow is able to accept a target application and proceed through successive stages of optimization, ultimately producing an optimized circuit compiled for an optimal ISA on an optimized processor. Objects are depicted as cuboids. A black arrow indicates that the performance of the target object can be evaluated based on the source objects, with the corresponding computational process shown in a yellow parallelogram. A green arrow indicates that the target object can be designed by adjusting the source objects, and the associated design process is represented in a green parallelogram. Multiple design processes can be linked together to form a co-design framework.
• Figure 2: Pictorial illustration of the superconducting quantum chip design workflow, including the key steps of the layout design ((a)-(d)), the EM field simulation (e), and the Hamiltonian derivation (f). An example of a real chip is shown in (g).
• Figure 3: The diagram of the design parameters on the Hamiltonian level in the quantum processor. The fidelity of the operation $F(\{d_i\},\{c_j\},\{e_k\})$ is related to three sets of parameters: device parameters, control parameters and decoherence parameters. The device and decoherence parameters may fluctuate due to instability in the fabrication. The resolution of the control parameters is limited by the instrument.
• Figure 4: Illustration of the decoherence related workflow, including the representation of decoherence, steps to determine the decoherence models and parameters and how they are used in QDA. For detailed description about how to verify the models and parameters, see \ref{['subsec:noise_extraction']}.
• Figure 5: A typical Workflow for Quantum Circuit Synthesis and Transpilation. The circuit synthesis and optimization stages aim to decompose circuits into 1Q and 2Q gates, with the goal of minimizing either the total gate count or circuit depth. The qubit mapping and routing stage bears similarities to register allocation and instruction scheduling in traditional computing; its core objective is to reduce routing overhead---specifically, the number of SWAP gates inserted. The final stage, known as the ISA rebase, gate scheduling, and optimization phase, involves translating the processed circuit into pulse sequences. Here, the primary desired outcome is minimizing the total pulse duration. Note that in some quantum SDKs such as Qiskit, the synthesis procedure may be considered as part of the transpilation process.

Theorems & Definitions (1)

• Conjecture 10.1