P4-TAS: P4-Based Time-Aware Shaper for Time-Sensitive Networking

TL;DR

This work addresses the challenge of achieving nanosecond-precision timing for TSN/DetNet traffic shaping by exposing and quantifying internal delays in hardware. It introduces P4-TAS, a P4-based TAS implementation on Intel Tofino 2 that uses a continuous stream of internally generated TAS control frames and a tGCL MAT to drive AFC-based queue state changes, while integrating PSFP and MPLS/TSN for DetNet translation. Key contributions include identification and measurement of internal delay sources (traffic generator accuracy, queue opening delay, and control traffic delay), a range-to-ternary method to increase time-resolution, and a detailed scalability assessment showing support for up to ~39k tGCL entries and ~8k streams, as well as competitive line-rate performance up to 400 Gb/s. The work provides a transparent view of timing behavior not typically disclosed by commercial platforms, enabling more predictable and robust schedule design for TSN/DetNet deployments and informing future hardware and scheduling algorithms.

Abstract

Time-Sensitive Networking (TSN) is a set of IEEE standards that extends Ethernet with real-time capabilities. Among its mechanisms, TSN can coordinate transmission times network-wide to minimize queueing, ensuring low latency and bounded delay. This coordination is computed offline and yields a network-wide schedule. The Time-Aware Shaper (TAS), implemented in TSN bridges, protects high-priority scheduled traffic from lower-priority (best-effort) flows by periodically opening and closing priority queues according to this schedule. Deterministic Networking (DetNet), standardized by the IETF, provides similar guarantees at Layer 3 and can leverage TSN mechanisms such as TAS for that purpose. Commercially available TSN-capable switches typically implement TAS in hardware but rarely disclose internal processing delays such as queue opening latency. Such information is essential for precise scheduling but largely unavailable to system designers. In this work, we present P4-TAS, a P4-based implementation of the TAS on a hardware switching ASIC. Our design introduces a novel approach for periodic queue control using a continuous stream of internally generated TAS control frames. We identify and quantify three sources of internal delay on a nanosecond scale which also exist in other implementations that directly affect the precision of executed schedules, providing transparency for future implementations and scheduling algorithms. Moreover, we provide an MPLS/TSN translation layer that enables P4-TAS to operate within DetNet environments, allowing TSN time-based traffic shaping to be carried over high-speed 400 Gb/s forwarding. Finally, we evaluate the scalability of P4-TAS and compare it to available TAS implementations.

Figures (16)

• Figure 1: The TAS shapes scheduled traffic by gating egress queues while PSFP polices stream conformance at the ingress qbvqci.
• Figure 2: The pipeline of the TNA.
• Figure 3: Concept of MAT in P4.
• Figure 4: Placement of P4-TAS in a DetNet environment using a TSN sub-layer.
• Figure 5: The tGCL of the TAS is modeled as a MAT. The generated TAS control traffic is matched in this table. As an action, the corresponding queue is opened or closed.