Addressable fault-tolerant universal quantum gate operations for high-rate lift-connected surface codes

TL;DR

This work shows that high-rate lift-connected surface (LCS) codes can support addressable, fault-tolerant universal quantum computation by constructing the full Clifford group via round-robin gates and enhancing them with flag-qubit fault-tolerance. For the $[[15,3,3]]$ LCS code, the authors realize deterministic FT Clifford gates and propose FT magic-state preparation to achieve Clifford+T universality, with circuit-level simulations yielding pseudothresholds in the $10^{-3}$ to $10^{-2}$ range. The study contrasts algorithmic fault tolerance, which leverages full circuit data for decoding, with gadget-based FT protocols, showing competitive performance and realistic resource overhead (roughly 33 qubits for full FT gates plus EC). The results indicate near-term feasibility for fault-tolerant logic in small LCS instances, and outline a path toward scaling to higher distances while acknowledging the potential scaling challenges of the leading-order fault-coefficient. Key contributions include: (i) a general method to implement all Clifford gates on LCS codes via a decode-transform-encode approach; (ii) explicit flag-based FT constructions for single- and two-qubit Clifford gates and FT magic-state preparation on the $[[15,3,3]]$ code; (iii) comprehensive numerical benchmarking under circuit-level depolarizing noise, with pseudothreshold estimates comparing AF and gadget FT schemes; and (iv) practical guidance for near-term experiments leveraging high-rate qLDPC codes.

Abstract

Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling $[[n, \mathcal{O}(n^{1/3}), \mathcal{O}(n^{1/3})]]$. In particular, LCS codes realize favorable instances with small numbers of qubits: For the $[[15,3,3]]$ LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set $\{\overline{H}_i, \overline{H}_i, \overline{C_i X_j}\}_{i,j \in (0,1,2)}$ based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in $d=3$ LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range $p_{\mathrm{th}} \approx 4.8\cdot 10^{-3}-1.2\cdot 10^{-2}$ for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.

Figures (18)

• Figure 1: a) Tanner graph of $\llbracket 15,3,3 \rrbracket$ Lift-connected surface code (LCS) and round-robin logical $\overline{H}$ gate. Circles represent data qubits, blue and solid squares the $Z$-stabilizers and red and dashed squares the $X$-stabilizers. This LCS code corresponds to three interconnected copies of $d=2$ surface codes. We indicate the support of the three logical $\overline{X}$- and logical $\overline{Z}$- operators by a yellow solid, green dotted and orange dashed border, respectively. b) For one logical operator we also show the targeted round-robin logical $\overline{H}$ gate. It consists of all-to-all $YCY$ and transversal physical $H$ and $Y$ gates on qubits in the support of the logical operator. In the main text, we explain how to render this logical gate circuit fault-tolerant.
• Figure 2: Flagging a $4$-body Pauli-$X$ measurement to catch correlated errors. a) An $X$-fault on the ancilla qubit after the second entangling $CX$ propagates to a weight-2 $XX$ error on the data qubits. b) We insert an identity measurement using an additional flag qubit. This does not change the original measurement, and as such, does not detect the fault. c) Commuting one gate through the second $CX$ can catch the $X$-fault as it now only propagates to the ancilla once and flips the flag-measurement.
• Figure 3: Two notions of fault-tolerant error-correction circuits we consider in this work. We consider a Clifford circuit with encoded state preparation ($\lhd$), logical single- and two qubit gates ($\Box$) and final measurements ($\rhd$). We denote error correction cycles by a green box. a) Traditional Gadget Fault Tolerance. Each gadget is independently decoded (dashed rectangle). For overall fault-tolerance, this requires a strictly fault-tolerant implementation of the gates with a fully fault-tolerant round of error correction after each logical gate. b) In Algorithmic Fault Tolerance, as much information as possible is included in the decoding. For the circuits considered, this can be all detector outcomes of the circuit, including final measurement. This can lead to reduced requirements on overhead of error correction cycles while staying fault tolerant, as indicated by thinner squares. For transversal algorithmic fault tolerance, this can be as low as $\Theta(1)$ rounds of syndrome measurements per logical gate zhou2025low.
• Figure 4: 1-Fault-tolerant error-correction protocol. Start by measuring the stabilizer generators with flags $\{S_i\}^f$, resulting in detector outcomes $\mathbf{d}^{(0)}$. If any detector has non-trivial outcome, we know some fault has occurred. A subsequent (non-flagged) stabilizer generator measurement acts as a noise-free round of stabilizer measurements in order $\mathcal{O}(p)$, allowing for unique identification of all $\mathcal{O}(p)$ faults. If all detectors have trivial outcome, the distinguishability of $\{S_i\}^f$ ensures that no or no uncorrectable fault has occurred. In that case, nothing has to be done.
• Figure 5: 1-Fault-tolerant gate protocol. Start by applying the (flagged) unitary gate $G^f$ that has a distinguishable fault set. If any of the detector outcomes $\mathbf{d}^{(0)}$ is non-trivial, a fault has occurred and a non-flagged round of stabilizer measurement is sufficient to correct all faults in order $\mathcal{O}(p)$. For a trivial detector outcome, we append a round of FT error correction, cf. protocol in Fig. \ref{['fig:ft_ec']}.