DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior

TL;DR

DR-GNN addresses the limitation of static circuit representations by learning dynamic RTL representations from an operator-level CDFG and input sequences. It trains via pre-training tasks on branch-hit and toggle-rate, using a semi-decoupled, position-aware GNN that leverages rotor-based embeddings to capture multi-cycle execution. The work introduces the DynamicRTL dataset (≈6.3k designs, ≈63k traces) and demonstrates state-of-the-art pre-training performance, plus strong transfer to downstream tasks like RTL-level power estimation and assertion prediction. The results indicate meaningful practical impact for early-design dynamic analysis and hardware verification, with a release fostering broader adoption.

Abstract

There is a growing body of work on using Graph Neural Networks (GNNs) to learn representations of circuits, focusing primarily on their static characteristics. However, these models fail to capture circuit runtime behavior, which is crucial for tasks like circuit verification and optimization. To address this limitation, we introduce DR-GNN (DynamicRTL-GNN), a novel approach that learns RTL circuit representations by incorporating both static structures and multi-cycle execution behaviors. DR-GNN leverages an operator-level Control Data Flow Graph (CDFG) to represent Register Transfer Level (RTL) circuits, enabling the model to capture dynamic dependencies and runtime execution. To train and evaluate DR-GNN, we build the first comprehensive dynamic circuit dataset, comprising over 6,300 Verilog designs and 63,000 simulation traces. Our results demonstrate that DR-GNN outperforms existing models in branch hit prediction and toggle rate prediction. Furthermore, its learned representations transfer effectively to related dynamic circuit tasks, achieving strong performance in power estimation and assertion prediction.

Figures (12)

• Figure 1: The overview of DynamicRTL. The framework prepares circuit training data, including CDFGs and simulation traces, and employs pre-training tasks to train the model. The learned representations are then used for downstream tasks.
• Figure 2: Comparison between statement-level CDFG and operator-level CDFG. In Verilog grammar, the operator <= denotes a non-blocking assignment to register.
• Figure 3: The overview of circuit dynamic behavior-aware DR-GNN model.
• Figure 4: Ablation Study. Branch hit and toggle rate prediction on different input encoding and aggregation mechanisms.
• Figure 5: Ablation Study. Branch hit and toggle rate prediction accuracy on different messaging mechanisms.