Event-Driven Digital-Time-Domain Inference Architectures for Tsetlin Machines

TL;DR

This work tackles the energy and latency challenges of edge inference by introducing a digital-time-domain architecture for Tsetlin Machines (TMs). It combines an asynchronous, clock-less controller with time-domain classification through delay-encoded arithmetic, using a Hamming-distance framework for multi-class TM and a differential-delay plus Leading-ones-Detector (LOD) scheme for CoTM. Key contributions include: (i) an asynchronous three-stage controller enabling elastic throughput, (ii) a time-domain classification path with a binary multiplication matrix, LOD delay extraction, differential delay accumulation, and WTA arbitration, and (iii) extensive functional verification and performance comparisons showing substantial energy efficiency gains and competitive throughput versus traditional digital baselines and prior accelerators. The results indicate that fully time-domain TM inference is highly suited for resource-constrained edge platforms, with CoTM benefitting from a hybrid digital-time-domain strategy that preserves signed-weight information while compressing delays for robust, low-power operation. Overall, the proposed approaches bridge conventional digital accelerators and emerging time-domain hardware, enabling scalable, energy-efficient edge ML deployments. $\hat{y}$ denotes the predicted class, and the HD-based decision and time-domain arguments are used to select it efficiently in hardware.

Abstract

Machine learning fits model parameters to approximate input-output mappings, predicting unknown samples. However, these models often require extensive arithmetic computations during inference, increasing latency and power consumption. This paper proposes a digital-time-domain computing approach for Tsetlin machine (TM) inference process to address these challenges. This approach leverages a delay accumulation mechanism to mitigate the costly arithmetic sums of classes and employs a Winner-Takes-All scheme to replace conventional magnitude comparators. Specifically, a Hamming distance-driven time-domain scheme is implemented for multi-class TMs. Furthermore, differential delay paths, combined with a leading-ones-detector logarithmic delay compression digital-time-domain scheme, are utilised for the coalesced TMs, accommodating both binary-signed and exponential-scale delay accumulation issues. Compared to the functionally equivalent, post-implementation digital TM architecture baseline, the proposed architecture demonstrates orders-of-magnitude improvements in energy efficiency and throughput.

Figures (8)

• Figure 1: Block diagram of the proposed architecture.
• Figure 2: Click element-based asynchronous pipeline.
• Figure 3: The hybrid digital-time domain architecture for CoTM classification.
• Figure 4: Differential delay path.
• Figure 5: Gate-level netlist of a Mutex