CADIC: Continual Anomaly Detection Based on Incremental Coreset

TL;DR

This paper tackles continual anomaly detection under dynamic data distributions by replacing task-specific memory banks with a single, fixed-size memory bank updated incrementally via an incremental coreset. It employs a ViT-based feature extractor and a nearest-neighbor scoring scheme on the shared coreset to detect anomalies, achieving strong performance on MVTec AD and VisA and demonstrating robustness in real-world settings like electronic paper inspection. The key contributions are the unified memory bank design, the incremental coreset update mechanism with efficient distance computations, and comprehensive empirical validation showing state-of-the-art results and good forgetting resistance. The approach has practical significance for industrial QA where new products arrive sequentially and scalable, task-free anomaly detection is required.

Abstract

The primary objective of Continual Anomaly Detection (CAD) is to learn the normal patterns of new tasks under dynamic data distribution assumptions while mitigating catastrophic forgetting. Existing embedding-based CAD approaches continuously update a memory bank with new embeddings to adapt to sequential tasks. However, these methods require constructing class-specific sub-memory banks for each task, which restricts their flexibility and scalability. To address this limitation, we propose a novel CAD framework where all tasks share a unified memory bank. During training, the method incrementally updates embeddings within a fixed-size coreset, enabling continuous knowledge acquisition from sequential tasks without task-specific memory fragmentation. In the inference phase, anomaly scores are computed via a nearest-neighbor matching mechanism, achieving state-of-the-art detection accuracy. We validate the method through comprehensive experiments on MVTec AD and Visa datasets. Results show that our approach outperforms existing baselines, achieving average image-level AUROC scores of 0.972 (MVTec AD) and 0.891 (Visa). Notably, on a real-world electronic paper dataset, it demonstrates 100% accuracy in anomaly sample detection, confirming its robustness in practical scenarios. The implementation will be open-sourced on GitHub.

Figures (8)

• Figure 1: Comparison of AD, existing CAD and the proposed CADIC pipeline. (a) Traditional embedding-based AD methods use separate memory banks, each task has its own individual memory bank. (b) Existing embedding-based CAD methods imply only one memory bank, but each task has a specific sub bank. (c) Our embedding-based CAD method (CADIC) utilizes a single memory bank, and all tasks share it.
• Figure 2: Framework for the proposed method.
• Figure 3: Illustration of the incremental coreset sampling.
• Figure 4: t-SNE visualization of features sampled from the MVTec AD dataset
• Figure 5: Time consumption curve for every 100 images sampled. The horizontal coordinate axis is the image batch number (each batch corresponds to 100 images), and the vertical coordinate axis is the time consumed (seconds).