A Dual-Memory Ferroelectric Transistor Emulating Synaptic Metaplasticity for High-Speed Reservoir Computing

TL;DR

This work presents a CMOS‑compatible ferroelectric transistor (FeFET) that simultaneously implements non‑volatile long‑term memory (LTM) through HZO polarization and volatile short‑term memory (STM) via overlap‑engineered non‑quasi‑static (NQS) channel dynamics. By programmatically tuning the LTM state, the device controls the STM sign and strength (PPF vs PPD) and achieves microsecond operation with low energy, enabling a compact physical reservoir computing (PRC) system that solves a second‑order nonlinear dynamic task using only 16 reservoir states. The FeFET reservoir demonstrates NMSEs on the order of $3.69\times10^{-3}$ (test) with $20\ \mu$s response and $1.5\times10^{-7}$ J per inference, representing a ~$10^3$× speedup and ~5× energy efficiency relative to prior approaches. These results establish general material‑design principles for dual‑memory neuromorphic hardware and offer an immediately manufacturable pathway toward energy‑efficient edge intelligence with potential CMOS+X heterogeneous integration across oxide semiconductors.

Abstract

The exponential growth of edge artificial intelligence demands material-focused solutions to overcome energy consumption and latency limitations when processing real-time temporal data. Physical reservoir computing (PRC) offers an energy-efficient paradigm but faces challenges due to limited device scalability and reconfigurability. Additionally, reservoir and readout layers require memory of different timescales, short-term and long-term respectively - a material challenge hindering CMOS-compatible implementations. This work demonstrates a CMOS-compatible ferroelectric transistor using hafnium-zirconium-oxide (HZO) and silicon, enabling dual-memory operation. This system exhibits non-volatile long-term memory (LTM) from ferroelectric HZO polarization and volatile short-term memory (STM) from engineered non-quasi-static (NQS) channel-charge relaxation driven by gate-source/drain overlap capacitance. Ferroelectric polarization acts as non-volatile programming of volatile dynamics: by modulating threshold voltage, the ferroelectric state deterministically switches the NQS time constant and computational behavior between paired-pulse facilitation (PPF) and depression (PPD). This establishes a generalizable material-design principle applicable to diverse ferroelectric-semiconductor heterostructures, extending beyond silicon to oxide semiconductors and heterogeneously-integrated systems. The device solves second-order nonlinear tasks with 3.69 x 10^-3 normalized error using only 16 reservoir states - ~5x reduction - achieving 20 us response time (~1000x faster) and 1.5 x 10^-7 J energy consumption, providing an immediately manufacturable pathway for neuromorphic hardware and energy-efficient edge intelligence.

Figures (16)

• Figure 1: A representation of a conventional reservoir and how it is converted into the FeFET reservoir. In the conventional approach (left), the reservoir is modeled as a recurrent neural network; the input weights ($W_{in}$) and the recurrent reservoir weights ($W$) remain fixed, while only the readout weights ($W_{out}$) are trained. In contrast, the FeFET reservoir (right) comprises heterogeneous FeFET devices exhibiting distinct behavior. The input sequence u(t) is first encoded into voltage signals, which drive the FeFET array. The resulting output currents are scaled according to device conductance to produce the reservoir states, which are then processed by the readout layer.
• Figure 2: (a) Cross-section of the planar FeFET device showing an overlap region of 3.5 $\mu$m $\times$ 50 $\mu$m between gate metal (W) and source/drain (n++) implant region forming a capacitor structure. (b) X-ray diffraction (XRD) spectrum of the 8 nm hafnium-zirconium-oxide (HZO) film after annealing. The prominent diffraction peak centered at approximately 30.4° corresponds to the (111) reflection of the ferroelectric orthorhombic phase. This confirms the successful crystallization of the HZO layer, which is essential for the ferroelectric behavior of the gate dielectric in the device. (c) A TEM image of the FeFET gate stack. The TEM clearly shows the crystalline nature of the HZO, with the repeating dot-like pattern arising from its polycrystalline structure. (d) $I_{d}$–$V_{gs}$ plot for various gate voltage sweeping ranges showing anticlockwise hysteresis modulating the threshold voltage based on gate polarization. Drain voltage is kept at 50 mV. (e) $I_{d}$–$V_{ds}$ plot for various gate voltages showing anticlockwise hysteresis that is only prominent for faster sweep speed (about 2 V/s) and higher gate voltage.
• Figure 3: (a) Current response to ten 10 $\mu$s rectangular voltage pulses of 1 V administered in close temporal proximity, separated by an inter-pulse interval of 10 $\mu$s. The pulses generate an amplified current response, illustrating the PPF of the FeFETs. Drain voltage pulse sequence showing PPF effect when the FeFET is polarized at +4 V on the gate side. (b) Drain voltage pulse sequence showing PPD effect when the FeFET is polarized at -4 V on the gate side. (c) Calculated percentage increase of drain current between the first and sixth pulses during the ten-pulse sequence. The percentage shows a positive increase in drain current for +4 V and +3 V gate polarization, while a decrease in drain current occurs at -4 V gate polarization. (d) To demonstrate the unique temporal dynamics of each FeFET device, we display representative experimental data for PPF for three planar devices with various channel lengths of 2, 3, and 5 $\mu$m. The inset displays a typical drain current response to two square voltage pulses administered in close temporal proximity, separated by an inter-pulse interval (IPI). The pulses generate an amplified current response, illustrating the PPF of the FeFET. Quantitatively, PPF is defined in terms of the peak drain current of the first pulse (A) and second pulse (B) as follows: PPF = (B - A)/A × 100%. The PPF values for the three planar devices of our FeFETs are then plotted against IPI. The voltage pulses employed were 15 $\mu$s in duration and rectangular waveforms with an amplitude of 1 V.
• Figure 4: Complete workflow solving the second-order dynamic nonlinear transfer function with our Si-FeFET devices.
• Figure 5: (a) Complete timeline of the 500-point training set measurements. (b) The pre-writing scheme of the 500-point training set measurements. The pre-writing scheme is utilized to account for the initialization of the device. (c) Section of the encoded voltage pulses and drain current response towards the end of the 500-point training set measurements. (d) Due to device heterogeneity, each FeFET feature in the reservoir exhibits different polarization states, and different feature combinations result in varying NMSE values. The plot illustrates how the statistical measures of NMSE change with the number of features, showing a clear decrease in NMSE as the number of features increases.