ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings

TL;DR

ZeroSim introduces a unified transformer-based approach for zero-shot analog circuit performance evaluation, addressing the bottleneck of SPICE-based evaluation and topology-specific predictors. By combining a large, diverse training corpus with unified topology embeddings and topology-conditioned parameter mapping, it achieves robust generalization to unseen topologies and parameter configurations without retraining. The method demonstrates superior accuracy over baselines and delivers substantial speedups in RL-based sizing workflows, underscoring practical impact for rapid analog design. Overall, ZeroSim advances scalable, plug-and-play circuit evaluation that can accelerate design cycles across diverse amplifier topologies.

Abstract

Although recent advancements in learning-based analog circuit design automation have tackled tasks such as topology generation, device sizing, and layout synthesis, efficient performance evaluation remains a major bottleneck. Traditional SPICE simulations are time-consuming, while existing machine learning methods often require topology-specific retraining or manual substructure segmentation for fine-tuning, hindering scalability and adaptability. In this work, we propose ZeroSim, a transformer-based performance modeling framework designed to achieve robust in-distribution generalization across trained topologies under novel parameter configurations and zero-shot generalization to unseen topologies without any fine-tuning. We apply three key enabling strategies: (1) a diverse training corpus of 3.6 million instances covering over 60 amplifier topologies, (2) unified topology embeddings leveraging global-aware tokens and hierarchical attention to robustly generalize to novel circuits, and (3) a topology-conditioned parameter mapping approach that maintains consistent structural representations independent of parameter variations. Our experimental results demonstrate that ZeroSim significantly outperforms baseline models such as multilayer perceptrons, graph neural networks and transformers, delivering accurate zero-shot predictions across different amplifier topologies. Additionally, when integrated into a reinforcement learning-based parameter optimization pipeline, ZeroSim achieves a remarkable speedup (13x) compared to conventional SPICE simulations, underscoring its practical value for a wide range of analog circuit design automation tasks.

Figures (5)

• Figure 1: The overall pipeline of ZeroSim. It first encodes circuit topology using independent structural encoding with hierarchical attention. Device parameters are then injected via cross-attention in the parameter-aware layers. A transformer decoder processes performance query tokens to generate final circuit performance predictions.
• Figure 2: The transformation of a transistor-level amplifier schematic into a graph-based topology representation. Each pin-level node and device is encoded into a structured graph, augmented with a global graph token to facilitate context-aware encoding.
• Figure 3: Comparison of few-shot learning accuracy across different fintuning dataset sizes against fully trained circuit topology baseline.
• Figure 4: t-SNE visualization of graph embeddings from the ZeroSim encoder for 500 randomly selected samples across 10 circuit topologies. Each color represents a different topology.
• Figure 5: Performance comparison of ZeroSim and SPICE simulation when adopted in the RL-based circuit sizing pipeline. The lines are averaged over 200-second window. ZeroSim's circuit parameters are re-evaluated by SPICE simulation for a fair FoM reward comparison. Reward is defined in AnalogGym li2024analoggym.