Dense packing of the surface code: code deformation procedures and hook-error-avoiding gate scheduling
Kohei Fujiu, Shota Nagayama, Shin Nishio, Hideaki Kawaguchi, Takahiko Satoh
TL;DR
This work addresses the high qubit overhead of surface-code quantum error correction by proposing dense packing of surface-code patches. It introduces a concrete code-deformation protocol to fuse patches into a densely packed configuration and a hook-error-avoiding CNOT scheduling to suppress error propagation, complemented by circuit-level Monte Carlo simulations. The results show that, as the code distance $d$ increases and the physical error rate $p$ decreases, the densely packed arrangement can achieve comparable or lower logical error rates than standalone patches, with asymptotic space savings of about $3/4$ per logical qubit. A conceptual hierarchical memory microarchitecture is proposed to exploit dense packing for long-term storage, highlighting practical significance for space-efficient fault-tolerant quantum computing.
Abstract
The surface code is one of the leading quantum error correction codes for realizing large-scale fault-tolerant quantum computing (FTQC). One major challenge in realizing surface-code-based FTQC is the extremely large number of qubits required. To mitigate this problem, fusing multiple codewords of the surface code into a densely packed configuration has been proposed. It is known that by using dense packing, the number of physical qubits required per logical qubit can be reduced to approximately three-fourths compared to simply placing surface-code patches side by side. Despite its potential, concrete deformation procedures and quantitative error-rate analyses have remained largely unexplored. In this work, we present a detailed code-deformation procedure that transforms multiple standard surface code patches into a densely packed, connected configuration, along with a conceptual microarchitecture to utilize this dense packing. We also propose a CNOT gate-scheduling for stabilizer measurement circuits that suppresses hook errors in the densely packed surface code. We performed circuit-level Monte Carlo noise simulation of densely packed surface codes using this gate scheduling. The numerical results demonstrate that as the code distance of the densely packed surface code increases and the physical error rate decreases, the logical error rate of the densely packed surface code becomes lower than that of the standard surface code. Furthermore, we find that only when employing hook-error-avoiding syndrome extraction can the densely packed surface code achieve a lower logical error rate than the standard surface code, while simultaneously reducing the space overhead.
