ReQISC: A Reconfigurable Quantum Computer Microarchitecture and Compiler Co-Design

TL;DR

ReQISC tackles the bottleneck in practical quantum computing by co-designing a fully expressive SU$(4)$ quantum instruction set with a time-optimal microarchitecture and an end-to-end compiler. It demonstrates that directly implementing arbitrary 2Q gates under a unified Hamiltionian with simple pulse controls can dramatically reduce gate durations, circuit depth, and qubit-routing overhead, while balancing calibration costs via program-aware and program-agnostic optimization passes. The framework combines a canonical SU$(4)$ representation through Weyl coordinates, a mirroring-based approach to near-identity gates, template-based and hierarchical synthesis, and topology-aware routing (mirroring-SABRE). Empirical results across 132 benchmarks show substantial improvements in pulse duration (average reductions up to ~68% versus CNOT-based baselines) and fidelity, with scalable compilation times, indicating practical feasibility for near-term and fault-tolerant quantum devices.

Abstract

The performance of current quantum hardware is severely limited. While expanding the quantum ISA with high-fidelity, expressive basis gates is a key path forward, it imposes significant gate calibration overhead and complicates compiler optimization. As a result, even though more powerful ISAs have been designed, their use remains largely conceptual rather than practical. To move beyond these hurdles, we introduce the concept of "reconfigurable quantum instruction set computers" (ReQISC), which incorporates: (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonians; (2) a compilation framework tailored to ReQISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations, a program-agnostic pass for aggressive circuit-level optimization, and an SU(4)-aware routing pass that minimizes hardware mapping overhead. We detail the hardware implementation to demonstrate the feasibility, in terms of both pulse control and calibration of this superior gate scheme on realistic hardware. By leveraging the expressivity of SU(4) and the time minimality realized by the underlying microarchitecture, the SU(4)-based ISA achieves remarkable performance, with a 4.97-fold reduction in average pulse duration to implement arbitrary 2Q gates, compared to the usual CNOT/CZ scheme on mainstream flux-tunable transmons. Supported by the end-to-end compiler, ReQISC outperforms the conventional CNOT-ISA, SOTA compiler, and pulse implementation counterparts, in significantly reducing 2Q gate counts, circuit depth, pulse duration, qubit mapping overhead, and program fidelity losses. For the first time, ReQISC makes the theoretical benefits of continuous ISAs practically feasible.

Figures (15)

• Figure 1: Advancing architectural support for quantum advantage.
• Figure 2: ReQISC workflow. It incorporates (1) the most performant (time-optimal realization) microarchitecture to engineer any arbitrary $\mathrm{SU}(4)$ gates given the hardware coupling Hamiltonian and (2) an end-to-end compilation framework with three-stage optimization passes to generate executable $\mathrm{SU}(4)$-based circuits. The $\mathrm{SU}(4)$ ISA is expressed as the $\{\mathrm{Can},\, \mathrm{U}3 \}$ gate set.
• Figure 3: The ReQISC microarchitecture (gate scheme) directly implements arbitrary 2Q gates in a unified control. Common 2Q coupling form and standard 1Q Rabi drives with control parameters $\Omega_1$, $\Omega_2$, $\delta$, $\tau$, are sufficient to generate an evolution locally equivalent to the target unitary $U$. With the additional 1Q corrections appended/prepended to the solved evolution $e^{-i\tau (H + H_1 + H_2)}$, the circuit in the right figure exactly implements $U$.
• Figure 4: Hardware implementation of the ReQISC microarchitecture. (a) 2Q gate mirroring. The near-identity corner with a $\mathcal{L}^1$ coordinate norm bounded by $r$ is mirrored to the corner near $\mathrm{SWAP}$. (b) Gate time landscape, computed under the $\mathrm{XY}$ coupling Hamiltonian $H=\frac{g}{2}(XX+YY)$, where the circle size indicates the corresponding gate duration within the Weyl chamber. (c-d): Pulse control subschemes, under $\mathrm{XY}$ and $\mathrm{XX}$ couplings, respectively. (e) Local drive amplitudes required for representative gate families. The scaling factor $s$ represents the specific equivalent canonical gate within the gate family, e.g., $\mathrm{B}^s \sim \mathrm{Can}(s\frac{\pi}{4},s\frac{\pi}{8},0)$. $\mathrm{iSWAP}$ family requires no local drives so it is not shown in the figure; $\mathrm{CNOT}$ family and $\mathrm{B}$ family require only one-side drive ($A_1\neq 0$); $\mathrm{SWAP}$ family requires both-side drives ($A_1, A_2 \neq 0$). Frequency-related quantities ($A_1$, $A_2$, $\delta$) are normalized by the coupling strength $g$.
• Figure 5: Example and pipeline of hierarchical synthesis (HS). (a) The original alu-v2_33 circuit is partitioned into 3 three-qubit blocks with #2Q equal to 1, 8, and 8. After approximate synthesis on the latter two blocks, each has 5 $\mathrm{SU}(4)$s. The overall #2Q is reduced from 17 to 11. (b) HS involves two-tier partitioning, followed by DAG compacting and conditional approximate synthesis.

Theorems & Definitions (4)

• Theorem 1
• Lemma 2: genAshN-ND
• Lemma 3: genAshN-EA+
• Corollary 4: genAshN-EA-