Automating Hardware Design and Verification from Architectural Papers via a Neural-Symbolic Graph Framework

TL;DR

This work proposes ArchCraft, a Framework that converts abstract architectural descriptions from academic papers into synthesizable Verilog projects with register-transfer level (RTL) verification, and proposes the first benchmark, \textbf{ArchSynthBench}, for synthesizing hardware from architectural descriptions.

Abstract

The reproduction of hardware architectures from academic papers remains a significant challenge due to the lack of publicly available source code and the complexity of hardware description languages (HDLs). To this end, we propose \textbf{ArchCraft}, a Framework that converts abstract architectural descriptions from academic papers into synthesizable Verilog projects with register-transfer level (RTL) verification. ArchCraft introduces a structured workflow, which uses formal graphs to capture the Architectural Blueprint and symbols to define the Functional Specification, translating unstructured academic papers into verifiable, hardware-aware designs. The framework then generates RTL and testbench (TB) code decoupled via these symbols to facilitate verification and debugging, ultimately reporting the circuit's Power, Area, and Performance (PPA). Moreover, we propose the first benchmark, \textbf{ArchSynthBench}, for synthesizing hardware from architectural descriptions, with a complete set of evaluation indicators, 50 project-level circuits, and around 600 circuit blocks. We systematically assess ArchCraft on ArchSynthBench, where the experiment results demonstrate the superiority of our proposed method, surpassing direct generation methods and the VerilogCoder framework in both paper understanding and code completion. Furthermore, evaluation and physical implementation of the generated executable RTL code show that these implementations meet all timing constraints without violations, and their performance metrics are consistent with those reported in the original papers.

Figures (20)

• Figure 1: A real-world example. Archcraft assists in automating the process of transforming hardware design concepts into fully synthesizable RTL code, reducing manual intervention and accelerating the design process.
• Figure 2: Overview of our ArchCraft framework with four phases. (1) Graphing Agent parses the paper into a formal architectural knowledge graph. (2) Symbolize Agent converts the graph nodes into a rigorous symbolic blueprint. (3) Coding Agent decoupledly generates synthesizable RTL and TBs from the symbolic blueprint. (4) Automatic execution of compilation and checking of grammar and logical issues, collects error reports, holds errors and related codes accountable, and collaboratively corrects them within a continuous feedback loop. Finally, both LLM and human experts evaluate the generated code to assess the overall effectiveness of the system. The generated RTL code is then synthesized into a hardware implementation for physical-level evaluation.
• Figure 3: Prompts for graphing papers.
• Figure 4: Prompts for graphing papers.
• Figure 5: Prompts for graphing papers.