Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration

TL;DR

The paper tackles pico-second timing on FPGA by addressing bin nonuniformity and missing codes through two hardware-independent post-processing methods: Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI). POR infers a partial order of time bins from code-density tests to recover missing codes, while ITI merges multiple calibrated tapped delay lines into a single, ordered delay chain, yielding a substantial resolution boost without relying on averaging. On a 16-nm FPGA, the approach delivers a measured resolution of $1.15$ ps with RMS $3.38$ ps, DNL in $[-0.43, 0.24]$ LSB and INL in $[-2.67, 0.15]$ LSB, outperforming several prior FPGA-based TDCs. The techniques are broadly applicable to precise delay calibration in programmable platforms and enable scalable, high-precision timing for diverse applications such as LiDAR, PET, QKD, and quantum information processing.

Abstract

We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.

Figures (9)

• Figure 1: TDC architecture overview. (a) Functional block diagram. The input pulse is shaped with a fixed duration defined by the Start and Stop signals. The time bins (D flip-flops) are sorted via POR (see Section \ref{['subsec:POR']}) based on code density test results. (b) Illustration of the $Z_3$ grouping used in POR. (c) Iterative Time-bin Interleaving (ITI) framework to combine multiple delay lines according to their calibrated bin times (see Section \ref{['subsec:ITI']}).
• Figure 2: Illustration of missing code formation due to bin sequence mismatch. (a) A mismatch between the perceived and actual ordering of time bins results from delay variation. (b) Two signals transitioning at the fourth (Blue) and fifth (Red) time bins. (c) Resulting OHCs from the two signals. Time bin 4 is never selected as the OHC output and is thus effectively skipped, resulting in a missing code.
• Figure 3: This is the partial order deduced from the tapped bins of (2,3,5,6,8) (alternatively, the missing codes of (1,4,7)) on a CARRY8 cell. The time axis is as drawn in the blue arrow. Bins expressed with black arrows do not have any restrictions on how early they can come.
• Figure 4: The percentage of tapped bins in each of the 12 segments by using POR for bin sequence calibration.
• Figure 5: Post-ITI bin width histograms for four TDLs reconstructed from bin-calibrated $\mathbf{Z}_3$ segments. Time bins with widths smaller than 0.2 ps were filtered out during the ITI process. Each subfigure shows the number of tapped bins relative to the total number of assigned bins (e.g. 1016/1016). Notably, ITI preserves the calibrated bin sequence and introduces no new missing codes, demonstrating its reliability as a non-destructive technique within the 0.2 ps filtering threshold.