iEEG Seizure Detection with a Sparse Hyperdimensional Computing Accelerator

TL;DR

This paper investigates energy-efficient, real-time iEEG seizure detection using sparse hyperdimensional computing. It introduces two hardware optimizations—Compressed IM (CompIM) and spatial bundling without thinning—to reduce binding energy and area. Algorithmic analysis shows that, with proper HV density tuning, sparse HDC can approach the performance of dense HDC while offering substantial hardware savings. Hardware experiments in a 16nm process demonstrate up to 7.5x energy and 3.24x area improvements over dense HDC, and 1.72x energy and 2.20x area improvements over naive sparse HDC, supporting the viability of smaller, longer-lasting brain implants.

Abstract

Implantable devices for reliable intracranial electroencephalography (iEEG) require efficient, accurate, and real-time detection of seizures. Dense hyperdimensional computing (HDC) proves to be efficient over neural networks; however, it still consumes considerable switching power for an ultra-low energy application. Sparse HDC, on the other hand, has the potential of further reducing the energy consumption, yet at the expense of having to support more complex operations and introducing an extra hyperparameter, the maximum hypervector density. To improve the energy and area efficiency of the sparse HDC operations, this work introduces the compressed item memory (CompIM) and simplifies the spatial bundling. We also analyze how a proper hyperparameter choice improves the detection delay compared to dense HDC. Ultimately, our optimizations achieve a 1.73x more energy- and 2.20x more area-efficient hardware design than the naive sparse implementation. We are also 7.50x more energy- and 3.24x more area-efficient than the dense HDC implementation. This work highlights the hardware advantages of sparse HDC, demonstrating its potential to enable smaller brain implants with a substantially extended battery life compared to the current state-of-the-art.

Figures (5)

• Figure 1: (a) High-level overview of iEEG algorithm with HDC and the main requirements, (b) sparse HDC classifier for iEEG system, (c) area and energy breakdown of the naive sparse HDC implementation.
• Figure 2: (a) Segmented shift binding and (b) shift binding.
• Figure 3: Overview of HW implementation of first part of baseline sparse HDC system (a) and of optimized sparse HDC system (b).
• Figure 4: Average seizure detection delay and detection accuracy for different maximum HV densities after bundling.
• Figure 5: Energy and area breakdown of the iEEG system, comparing dense and sparse HDC baselines with our optimizations.