Quantum Data Representation via Circuit Partitioning and Reintegration

TL;DR

This work presents shardQ, a hardware-aware quantum data encoding framework that partitions large encoder circuits using SparseCut, compiles subcircuits with matrix-product-state methods, and globally reconstructs results via quasi-probability decomposition. By aligning cuts with the hardware coupling map and leveraging efficient MPS-based compilation, shardQ reduces end-to-end error while controlling classical postprocessing overhead, achieving about a 15% fidelity improvement on IBM QPUs. The approach is demonstrated on quantum image encoding benchmarks and analyzed for scalability, showing two cuts as the optimum trade-off between error mitigation and computational overhead. The method advances toward fault-tolerant regimes by enabling scalable, HPC-integrated quantum data processing on NISQ devices and provides a practical route for integrating quantum encoders into larger quantum algorithms.

Abstract

Quantum data encoding (QDE) enables faster com-putations than classical algorithms through superposition and en-tanglement. Circuit cutting and knitting are effective techniques for ameliorating current noisy quantum processing unit (QPUs) errors via a divide-and-conquer approach that splits quantum circuits into subcircuits and recombines them using classical postprocessing. Unfortunately, the existing QDE frameworks fail to consider quantum hardware limitations, such as the topology of the chip. Designing a computation model that supports the algorithm level of quantum computation and optimizes non-all-to-all connected quantum circuit simulations remains underde-veloped. In this study, we introduce shardQ, a method that leverages the SparseCut algorithm with matrix product state (MPS) compilation and a global knitting technique to mitigate the quantum error rates. This method elucidates the optimal trade-off between the computational time and error rate for quantum encoding with a theoretical proof, evidenced by an ablation analysis using an IBM Heron-type QPUs with 15% error reduction. This study also presents the results of quantum image encoding readiness. The proposed model advances the current quantum computation towards the fault-tolerant regime as QDE is the input of grand unified quantum algorithms.

Figures (10)

• Figure 1: Overview of the proposed method compared with conventional quantum data encoding techniques.
• Figure 2: The generic example of cutting two qubit gates into separate one qubit gates. Note that, the right side only shows one of the subcircuits.
• Figure 3: The shardQ protocol is outlined as follows: Initially, the original data encoder circuit employs the SparseCut algorithm to divide the circuit into subcircuits ($SC$). Subsequently, approximate quantum compilation is used to transpile these subcircuits into the MPS. The ansatze are executed on the QPU, where index $i$ denotes the partition and $j$ represents the decomposed gates. Ultimately, the results are globally reconstructed into classical tensor data using local saved intermediate results.
• Figure 4: Example of three-by-three tensor encoder circuit cutting paradigm. The scissors were placed under the longest entanglement gate, corresponding to the physical qubit mapping, as shown in \ref{['fig:coupling']}. We only show the first data block, as indicated by the grey dashed box. We refer to the remaining encoding blocks in Fig. 1 (c) jan1. Note that, each data qubit ($q_3, q_4, q_5$) corresponding to first encoded dimension P with the address qubit encoded position as the rotation parameters noted by the indexes of P.
• Figure 5: The three-by-three tensor encoder physical qubit mapping diagram. We denote the address qubits corresponding to $q_0, q_1, q_2$ in \ref{['fig:qcrank_cut']} by the blue-shaded area. The yellow area represents the data qubits $q_3, q_4, q_5$. The longest entanglement cut is $q_0$ (the first address qubit) and $q_5$ (third data qubit) shown in the dashed diagonal lines.

Theorems & Definitions (2)

• Definition 1: QDP overhead for CX gate
• Definition 2