Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

FPGA-Based Real-Time Waveform Classification

Alperen Aksoy, Ilja Bekman, Chimezie Eguzo, Christian Grewing, Andre Zambanini

TL;DR

This work addresses real-time waveform classification for SiPM readout on FPGAs by proposing a LUT-based binary neural network with $2$-bit neurons and $2$-bit weights, implemented via a $4\times4$ CAM to avoid multipliers and achieve fast inference. The network is trained with a genetic algorithm using the DEAP framework, optimizing for accuracy while promoting sparsity, and evaluated against CNN baselines (FINN and hls4ml). While the GA-trained BNNs offer lower accuracy, they provide latency compatible with dead-time-free online processing and a compact hardware footprint, highlighting a viable path for hardware-friendly online event tagging. The work also delivers a self-contained VHDL-NN code generator and a Python package (HCL4BNN_2025) to facilitate FPGA deployments and further optimizations, with suggested future directions including segment-wise frame processing and hybrid optimization strategies.

Abstract

For self-triggered readout of SiPM sum signals, a waveform classification can aid a simple threshold trigger to reliably extract calorimetric particle hit information online at an early stage and thus reduce the volume of transmitted data. Typically, the ADC data acquisition is based on FPGAs for edge data processing. In this study, we consider look-up-table-based neural-networks and address challenges of binary multi-layer neural networks' layout, footprint, performance and training. We show that these structures can be trained using a genetic algorithm and achieve the inference latency compatible with dead-time free processing online.

FPGA-Based Real-Time Waveform Classification

TL;DR

This work addresses real-time waveform classification for SiPM readout on FPGAs by proposing a LUT-based binary neural network with -bit neurons and -bit weights, implemented via a CAM to avoid multipliers and achieve fast inference. The network is trained with a genetic algorithm using the DEAP framework, optimizing for accuracy while promoting sparsity, and evaluated against CNN baselines (FINN and hls4ml). While the GA-trained BNNs offer lower accuracy, they provide latency compatible with dead-time-free online processing and a compact hardware footprint, highlighting a viable path for hardware-friendly online event tagging. The work also delivers a self-contained VHDL-NN code generator and a Python package (HCL4BNN_2025) to facilitate FPGA deployments and further optimizations, with suggested future directions including segment-wise frame processing and hybrid optimization strategies.

Abstract

For self-triggered readout of SiPM sum signals, a waveform classification can aid a simple threshold trigger to reliably extract calorimetric particle hit information online at an early stage and thus reduce the volume of transmitted data. Typically, the ADC data acquisition is based on FPGAs for edge data processing. In this study, we consider look-up-table-based neural-networks and address challenges of binary multi-layer neural networks' layout, footprint, performance and training. We show that these structures can be trained using a genetic algorithm and achieve the inference latency compatible with dead-time free processing online.

Paper Structure

This paper contains 5 sections, 2 equations, 3 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Binary Neural Network
  3. Genetic Algorithm
  4. Results of Training
  5. Conclusion and Outlook

Figures (3)

  • Figure 1: Comparison of implementation flow for NNs on FPGAs: Quantization aware training (above) vs. Hardware-constrained learning (below).
  • Figure 2: Simulated SiPM signal examples. Left: simple "Good"; Right: double "Ugly" Leone1966
  • Figure 3: (left) Best accuracy progression per generation from several GA runs; (right) Best accuracy and Size (number of "0"-weights) progression per generation for one longer GA run.