AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM

TL;DR

This paper tackles IR-drop in high-performance SRAM PIM by proposing AIM, a software-and-hardware co-design that ties workload characteristics to IR-drop via architecture-level metrics Rtog and HR. It combines offline HR optimization methods (Lower Hamming Rate and Weight Distribution Shift) with runtime hardware control (IR-Booster) and HR-aware task mapping to adapt DVFS-like behavior to IR-drop margins. Post-layout results on a 7nm 256-TOPS PIM show up to 69.2% IR-drop mitigation, up to 2.29× energy efficiency, and up to 1.15× speedup, with modest area/power overhead. Collectively, AIM demonstrates a practical, scalable path to architecture-level IR-drop mitigation that preserves accuracy while boosting performance and energy efficiency in SRAM PIM and potentially other AI accelerators.

Abstract

SRAM Processing-in-Memory (PIM) has emerged as the most promising implementation for high-performance PIM, delivering superior computing density, energy efficiency, and computational precision. However, the pursuit of higher performance necessitates more complex circuit designs and increased operating frequencies, which exacerbate IR-drop issues. Severe IR-drop can significantly degrade chip performance and even threaten reliability. Conventional circuit-level IR-drop mitigation methods, such as back-end optimizations, are resource-intensive and often compromise power, performance, and area (PPA). To address these challenges, we propose AIM, comprehensive software and hardware co-design for architecture-level IR-drop mitigation in high-performance PIM. Initially, leveraging the bit-serial and in-situ dataflow processing properties of PIM, we introduce Rtog and HR, which establish a direct correlation between PIM workloads and IR-drop. Building on this foundation, we propose LHR and WDS, enabling extensive exploration of architecture-level IR-drop mitigation while maintaining computational accuracy through software optimization. Subsequently, we develop IR-Booster, a dynamic adjustment mechanism that integrates software-level HR information with hardware-based IR-drop monitoring to adapt the V-f pairs of the PIM macro, achieving enhanced energy efficiency and performance. Finally, we propose the HR-aware task mapping method, bridging software and hardware designs to achieve optimal improvement. Post-layout simulation results on a 7nm 256-TOPS PIM chip demonstrate that AIM achieves up to 69.2% IR-drop mitigation, resulting in 2.29x energy efficiency improvement and 1.152x speedup.

Figures (22)

• Figure 1: SRAM PIM and data placement
• Figure 2: (a) IR-drop (b) Static and dynamic current
• Figure 3: Normalized IR-drop at different workloads
• Figure 4: Correlation of IR-drop and Rtog
• Figure 5: Rtog distribution: HR dominates the maximum of Rtog and HR optimization reduces overall Rtog