Self-correcting High-speed Opto-electronic Probabilistic Computer

TL;DR

This work tackles the challenge of scalable, energy-efficient probabilistic computing by introducing a self-correcting, high-speed optoelectronic processor that integrates SDI quantum photonic p-bits with a robust electronic control stack. The architecture enables large-scale networks (64k p-bits demonstrated) with real-time self-certification and error correction, delivering orders-of-magnitude improvements in speed and energy per flip over MTJ-based approaches. Key contributions include the SDI-based photonic p-bit design, FPGA-backed control for large networks, and empirical validation of high-speed operation and reliable performance across varying conditions. The findings suggest significant practical impact for combinatorial optimization, machine learning, and complex-system modeling, with clear paths toward further scaling and hardware optimization.

Abstract

We present a novel self-correcting, high-speed optoelectronic probabilistic computer architecture that leverages source-device independent (SDI) quantum photonic p-bits integrated with robust electronic control. Our approach combines the intrinsic randomness and high bandwidth of quantum photonics with the programmability and scal- ability of classical electronics, enabling efficient and flexible probabilistic computation. We detail the design and implementation of a prototype system based on photonic integrated circuits and FPGA-based control, capable of implementing and manipulating 64000 logical p-bits. Experimental results demonstrate that our architecture achieves a flip rate of 2.7 x 10^9 flips/s with an energy consumption of 4.9 nJ/flip, representing nearly three orders of magnitude improvement in speed and energy efficiency compared to state-of-the-art magnetic tunnel junc- tion (MTJ) based systems. Furthermore, the SDI protocol enables real-time self-certification and error correction, ensuring reliable operation across a wide range of conditions and solving the problem of hardware variability as the number of p-bits scale. Our results establish quantum photonic p-bits as a promising platform for scalable, high-performance probabilistic computing, with significant implications for combinatorial optimization, machine learning, and complex system modeling.

Figures (14)

• Figure 1: (a) Plot showing the non-linear impact that the bias has on the state of the p-bit. (b) Histogram plots showing the effect of the bias on the probabilities of the state of the p-bit. As can be seen clearly across the different subplots, as the input bias $I$ increases in the value the p-bit is biased from being always in the $-1$ state to being always in the $+1$ state passing through the equally balanced state when in the input bias is nil.
• Figure 2: Diagram showing a few examples for applications that can leverage the concepts and tools of probabilistic computing and outlining which categories they fit into.
• Figure 3: Diagram of the quantum photonic p-bit optoelectronic architecture and its essential components.
• Figure 4: (a) Diagram of the simplest setup for a difference detection-based QRNG where a source of photonic quantum states is combined with a beamsplitter with splitting ratio $r$ and a pair of photodetectors that are balanced. (b) Probability distribution for the number of photons detected at Detector A at different values of the beamsplitter's splitting ratio $r$.
• Figure 5: A schematic diagram showing the complete architecture of the source-device independent photonic p-bit. (a) Photonic sub-system: Similar to the setup in Fig.\ref{['fig:basic-qrng']}, the basics concepts of the source of randomness for the p-bit remain the same however we now do not make any assumptions about the input state emanating from the photonic source keeping it much more flexible. (b) Electronic sub-system: This subsystem performs the sum and difference operations (performed at (c)) on the outputs from the photodetectors, essential for the SDI protocol, these signals are enhanced using a transimpedance amplifier before being digitised.