Advancements and future expansions of the Caribou DAQ system

TL;DR

The paper addresses the need for a flexible and reusable DAQ for rapid prototyping and test-beam characterization of silicon pixel detectors. It presents Caribou, combining a CaR board with a Zynq SoC, and shared firmware and software stacks (Boreal and Peary) to enable modular, scalable detector readout. Key contributions include hardware validation of CaR v1.5 and the CaR v2 test board, the Boreal IP-module framework for common FPGA components, and a redesigned Peary software architecture with a Hardware Abstraction Layer that supports multiple Zynq platforms. The results demonstrate a pathway to a robust, maintainable DAQ platform capable of supporting a broad set of silicon pixel detector prototypes across experiments. The work positions Caribou as a scalable platform for rapid detector qualification and test-beam characterization across international collaborations.

Abstract

Caribou is a versatile data acquisition (DAQ) system developed within several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, and Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It combines a custom Control and Readout (CaR) board with a Xilinx Zynq System-on-Chip (SoC) running project-wide shared firmware and software stacks. The system architecture emphasizes reusability, flexibility, and ease of integration. The CaR board provides essential interfaces such as programmable power supplies, voltage and current references, high-speed ADCs, and configurable I/O lines for detector control and readout. The SoC runs an embedded Linux distribution built with PetaLinux and integrates two main components: Peary, a C++ embedded DAQ application providing hardware abstraction, configuration management, logging, and multi-device control through Command Line (CLI) and Python interfaces; and Boreal, a common Caribou FPGA firmware framework offering reusable modules and automated build workflows for user-specific bit files. The next major milestone in Caribou's evolution is the transition to version 2.0, based on a Zynq UltraScale+ System-on-Module (SoM) architecture. This paper presents the recent progress and future prospects of the project and describes recent hardware, firmware, and software developments preparing the system for the upcoming CaR board v2.0.

Figures (3)

• Figure 1: Block diagram of the Caribou hardware architecture
• Figure 2: Pictures of the CaR board v1.5 validation setup (a) and the v2.0 test board (b)
• Figure 3: Simplified UML diagram of the revised Peary architecture