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Challenges and strategies in verification of FastRICH ASIC for the LHCb RICH detector

M. Lupi, R. Ballabriga, F. N. Bandi, G. Bergamin, D. Ceresa, D. Gascon, S. Gomez, J. Kaplon, R. Manera, J. Mauricio, A. Paternò, D. Peninon-Herbaut, A. Pulli, S. Scarfì, G. J. Wegrzyn, K. Wyllie

TL;DR

The paper addresses verification challenges for a high-precision, triggerless readout ASIC (FastRICH) intended for the LHCb RICH LS3 upgrades. It presents a coverage-driven, UVM-based verification strategy that accounts for extreme timing precision ($25~\mathrm{ps}$) and asynchronous TDC operation by using metastability-aware RTL models and an approximate scoreboarding method. The study demonstrates that FastRICH meets performance across the full occupancy range, validating TDC timing and readout under stress and SEE conditions. The approach offers a practical blueprint for verifying triggerless, fast-timing ASICs in high-energy physics, with lessons on metastability modeling and robust scoreboarding that can inform future developments.

Abstract

The FastRICH ASIC provides high-precision, triggerless readout for the LS3 Enhancements and Upgrades II of the LHCb RICH detector. The demands of continuous data acquisition and varying hit rates across the detector impose unique challenges on the ASIC's design and verification. This work presents the verification strategy for FastRICH, focusing on functional correctness, timing performance, and operational robustness. The methodology includes simulations across occupancy scenarios, validation of timing precision, and stress testing under pile-up and high-rate conditions. Results demonstrate that FastRICH meets its performance requirements over the full range of expected occupancies. Key design and verification challenges specific to triggerless, fast-timing ASICs are discussed, along with lessons learned for future developments.

Challenges and strategies in verification of FastRICH ASIC for the LHCb RICH detector

TL;DR

The paper addresses verification challenges for a high-precision, triggerless readout ASIC (FastRICH) intended for the LHCb RICH LS3 upgrades. It presents a coverage-driven, UVM-based verification strategy that accounts for extreme timing precision () and asynchronous TDC operation by using metastability-aware RTL models and an approximate scoreboarding method. The study demonstrates that FastRICH meets performance across the full occupancy range, validating TDC timing and readout under stress and SEE conditions. The approach offers a practical blueprint for verifying triggerless, fast-timing ASICs in high-energy physics, with lessons on metastability modeling and robust scoreboarding that can inform future developments.

Abstract

The FastRICH ASIC provides high-precision, triggerless readout for the LS3 Enhancements and Upgrades II of the LHCb RICH detector. The demands of continuous data acquisition and varying hit rates across the detector impose unique challenges on the ASIC's design and verification. This work presents the verification strategy for FastRICH, focusing on functional correctness, timing performance, and operational robustness. The methodology includes simulations across occupancy scenarios, validation of timing precision, and stress testing under pile-up and high-rate conditions. Results demonstrate that FastRICH meets its performance requirements over the full range of expected occupancies. Key design and verification challenges specific to triggerless, fast-timing ASICs are discussed, along with lessons learned for future developments.

Paper Structure

This paper contains 7 sections, 2 figures, 1 algorithm.

Table of Contents

  1. Introduction
  2. FastRICH ASIC
  3. Verification Strategy
  4. Checker strategies
  5. Verification of TDC timing performance
  6. Verification of readout performance
  7. Conclusions

Figures (2)

  • Figure 1: The FastRICH ASIC is composed of 16 channels, each with a dedicated digital processing. The variable-length data packets are processed, strictly in order, in the packet processor and frame builder. Before being streamed on the serial links the frames are encapsulated in the Aurora protocol.
  • Figure 2: TDC dead time scan. The requirement of being able to readout two hits in two consecutive BX translates in a TDC deadtime smaller than $18.87 ns$, i.e. a $25ns$, a full BX, minus the maximum time gate duration, $6.25 ns$. This corresponds to two hits in subsequent BXs, where the first hit is at the end of the time gate and the second hit is at the beginning of the time gate, in the subsequent BX. Here it can be observed that all the channels, in different colors, are well within the required limit and that they all behave consistently.