Analytical Modeling of Asynchronous Event-Driven Readout Architectures Using Queueing Theory

TL;DR

The paper addresses the challenge of predicting performance for asynchronous event-driven readout with arbiter trees. It develops an analytical model treating the root as an $\text{M/D/1}$ queue with deterministic quantum $T$ and per-source one-slot gating, yielding a closed-form expression for the mean sojourn time $\mathbb{E}[S_t]$ and self-consistent relations among admitted rate, loss, utilization, and latency. Validation against post-layout EDWARD prototypes and simulations shows the model accurately reproduces latency growth and saturation at $1/T$ across light to heavy traffic, outperforming $M/G/1/K$ and Engset abstractions. The framework enables rapid design-time sizing and tiling decisions, showing that partitioning into tiles reduces arbitration depth and $\tau_0$, lowers loss, and improves latency while allowing throughput to add across tiles. This work provides a practical, algebraic tool linking architectural parameters to performance metrics for scalable event-driven readouts.

Abstract

Event-driven imagers and sensor arrays commonly employ asynchronous arbiter trees with a synchronous acknowledge to serialize requests. We present an analytical framework that models the root as an \(M/D/1\) queue with deterministic quantum \(T\) and implements losses at the sources through one-slot gating. The admitted rate, loss probability, utilization, and mean sojourn time are coupled by self-consistent relations; a closed form for \(\mathbb{E}[S_t]\) separates fixed path delay \(τ_0\) from queueing effects. The framework matches post-layout results of a physical prototype over light to heavy traffic, reproducing saturation at \(1/T\) and the observed latency growth, while classical \(M/G/1/K\) and Engset-type abstractions diverge at higher occupancy. Because all relations are algebraic, they enable rapid sizing at design time, including the impact of partitioning into independent tiles: reducing fan-in lowers arbitration depth and \(τ_0\), decreases loss, and improves latency at fixed \(T\), with throughput adding across tiles. The model thereby links architectural parameters to performance metrics and supports selection of acknowledge period, tiling, and link count under practical constraints.

Figures (7)

• Figure 1: Asynchronous request/acknowledge handshake in the EDWARD architecture. Three pixels (a -- c) issue requests, and arbitration gates the global acknowledge ack to produce per-winner signals acki[k]. Only the granted pixel observes the two same-polarity edges required to start and complete a transfer. The data bus (dbus) carries each pixel's payload in non-overlapping windows (a -- c). Unassigned intervals (default) correspond to idle bus states, while hatched regions denote short bus turnaround times. The latch marks sampling instants used by the serializer -- one completion is available per server quantum $T$.
• Figure 2: Binary arbiter cell based on Seitz mutexes. Left: child requests (req0, req1) are resolved into one-hot outputs (freq0, freq1). Right: per-branch acknowledge interlocks qualify local requests with the ack to prevent in-cell races or glitches. OR/AND networks form the upward propagated request and the gated acknowledges toward the children Gorni_2022.
• Figure 3: Two-stage arbitration tree. Stage 0 cells arbitrate leaf pairs, and Stage 1 arbitrates between their winners, forming the complete request/acknowledge hierarchy.
• Figure 4: Timing of a four-leaf arbiter tree under overlapping requests. Labels 1--4 denote request arrivals. The actual service sequence is 1--3--2--4. Orange asterisks mark pixel-level actions triggered by the acknowledge edges.
• Figure 5: Distribution of the service latency $S_t$ for a single isolated pixel. The histogram’s position and width provide estimates of the intrinsic request/acknowledge path delay $\tau_0$ and timing jitter, independent of inter-pixel contention Gorni_FEE2023.