Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM

Deyang Yu, Chenchen Liu, Chuanjie Zhang, Xiao Fang, Weisheng Zhao

TL;DR

The paper addresses the energy inefficiency of conventional analog CIM by introducing an event-driven spiking CIM macro built on SOT-MRAM. It presents a 32 Kb crossbar (128×128) of 3T-2MTJ cells, along with a Spike Modulation Unit and an Output Spike Generator to perform matrix-vector multiplication via spike timing, avoiding DAC/ADC overhead. The readout uses a Clamping&CM circuit and fixed-current charging to maintain linearity, achieving up to $243.6$ TOPS/W at 8-bit precision in 28 nm technology, with $T_{out}$ linearly related to the weighted sum of inputs. The proposed approach yields substantial energy savings and robust accuracy, offering a scalable pathway for low-power CIM in next-generation neural accelerators.

Abstract

The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit- Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is (en) decoded as spikes using lightweight circuits, eliminating the need for conventional area- and powerintensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs.

An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM

TL;DR

The paper addresses the energy inefficiency of conventional analog CIM by introducing an event-driven spiking CIM macro built on SOT-MRAM. It presents a 32 Kb crossbar (128×128) of 3T-2MTJ cells, along with a Spike Modulation Unit and an Output Spike Generator to perform matrix-vector multiplication via spike timing, avoiding DAC/ADC overhead. The readout uses a Clamping&CM circuit and fixed-current charging to maintain linearity, achieving up to TOPS/W at 8-bit precision in 28 nm technology, with linearly related to the weighted sum of inputs. The proposed approach yields substantial energy savings and robust accuracy, offering a scalable pathway for low-power CIM in next-generation neural accelerators.

Abstract

The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit- Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is (en) decoded as spikes using lightweight circuits, eliminating the need for conventional area- and powerintensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs.

Paper Structure

This paper contains 12 sections, 2 equations, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Motivation
  3. Conventional SOT-MRAM-based Analog Computing
  4. Related Works on Spiking Processing
  5. The Proposed SOT-MRAM Macro
  6. 3T-2MTJ Memory Cell
  7. Spike Modulation Unit
  8. Output Spike Generator
  9. Evaluation
  10. Energy Efficiency Analysis and Comparison
  11. Computing Linearity and Accuracy
  12. Conclusion

Figures (7)

  • Figure 1: (a) Conventional SOT-MRAM-based CIM designs; (b) Example of a SOT-MRAM cell implementation in 2T-3MTJ structure.
  • Figure 2: Overall architecture of the proposed spike-based MRAM CIM macro.
  • Figure 3: (a) Schematic of spike modulation unit; (b) Formation of Event_sig; (c) Transient simulation of spike modulation unit.
  • Figure 4: Schematics of output spike generator: (a) clamping&current mirror; (b) comparator block; (c) spike generator.
  • Figure 5: Transient simulation results of proposed design.
  • ...and 2 more figures