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Digit-Recurrence Posit Division

Raul Murillo, Julio Villalba-Moreno, Alberto A. Del Barrio, Guillermo Botella

TL;DR

This work adapts digit-recurrence division to Posit arithmetic, introducing the first radix-4 implementation and a set of hardware optimizations to reduce latency and energy. It combines redundant residual representations, on-the-fly quotient conversion, and operand scaling to streamline the division process across Posit widths, validated by synthesis in a 28 nm flow. Across 16-, 32-, and 64-bit Posits, radix-4 designs consistently reduce iteration counts and latency, achieving up to ~80% energy savings with modest area overhead relative to prior methods. The results demonstrate that radix-4 digit-recurrence division is a viable, high-performance approach for Posit units, offering substantial improvements for future PAU designs in RISCV/RISC architectures, with quantitative gains over existing digit-recurrence and Newton-Raphson-based dividers. The work further provides a detailed account of initialization, selection functions, and termination, enabling reproducible hardware realizations and guiding design choices for high-speed, low-power posit arithmetic cores.

Abstract

Posit arithmetic has emerged as a promising alternative to IEEE 754 floating-point representation, offering enhanced accuracy and dynamic range. However, division operations in posit systems remain challenging due to their inherent hardware complexity. In this work, we present posit division units based on the digit-recurrence algorithm, marking the first implementation of radix-4 digit-recurrence techniques within this context. Our approach incorporates hardware-centric optimizations including redundant arithmetic, on-the-fly quotient conversion, and operand scaling to streamline the division process while mitigating latency, area, and power overheads. Comprehensive synthesis evaluations across multiple posit configurations demonstrate significant performance improvements, including more than 80% energy reduction with small area overhead compared to existing methods, and a substantial decrease in the number of iterations. These results underscore the potential of our adapted algorithm to enhance the efficiency of posit-based arithmetic units.

Digit-Recurrence Posit Division

TL;DR

This work adapts digit-recurrence division to Posit arithmetic, introducing the first radix-4 implementation and a set of hardware optimizations to reduce latency and energy. It combines redundant residual representations, on-the-fly quotient conversion, and operand scaling to streamline the division process across Posit widths, validated by synthesis in a 28 nm flow. Across 16-, 32-, and 64-bit Posits, radix-4 designs consistently reduce iteration counts and latency, achieving up to ~80% energy savings with modest area overhead relative to prior methods. The results demonstrate that radix-4 digit-recurrence division is a viable, high-performance approach for Posit units, offering substantial improvements for future PAU designs in RISCV/RISC architectures, with quantitative gains over existing digit-recurrence and Newton-Raphson-based dividers. The work further provides a detailed account of initialization, selection functions, and termination, enabling reproducible hardware realizations and guiding design choices for high-speed, low-power posit arithmetic cores.

Abstract

Posit arithmetic has emerged as a promising alternative to IEEE 754 floating-point representation, offering enhanced accuracy and dynamic range. However, division operations in posit systems remain challenging due to their inherent hardware complexity. In this work, we present posit division units based on the digit-recurrence algorithm, marking the first implementation of radix-4 digit-recurrence techniques within this context. Our approach incorporates hardware-centric optimizations including redundant arithmetic, on-the-fly quotient conversion, and operand scaling to streamline the division process while mitigating latency, area, and power overheads. Comprehensive synthesis evaluations across multiple posit configurations demonstrate significant performance improvements, including more than 80% energy reduction with small area overhead compared to existing methods, and a substantial decrease in the number of iterations. These results underscore the potential of our adapted algorithm to enhance the efficiency of posit-based arithmetic units.

Paper Structure

This paper contains 24 sections, 20 equations, 9 figures, 4 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Background
  3. Posit Arithmetic
  4. Related Work
  5. Digit-Recurrence Posit Division Algorithm
  6. Fractional division algorithm
  7. Optimizations of the algorithm
  8. Using redundant representation for the residual
  9. Fast sign and zero detection of the final residual
  10. On-the-fly conversion
  11. Operands scaling
  12. Initialization process
  13. Selection function
  14. Radix-2 with non-redundant residual
  15. Radix-2 with redundant residual
  16. ...and 9 more sections

Figures (9)

  • Figure 1: Generic $n$-bit posit binary encoding.
  • Figure 2: Basic scheme for posit division.
  • Figure 3: Basic modules and timing of division by digit recurrence.
  • Figure 4: Synthesis results of combinational 16-bit posit dividers.
  • Figure 5: Synthesis results of combinational 32-bit posit dividers.
  • ...and 4 more figures