Multiplexed double-transmon coupler scheme in scalable superconducting quantum processor

TL;DR

This work tackles control-line scalability and $ZZ$ crosstalk in superconducting qubits by introducing a multiplexed double-transmon coupler (DTC) that shares a single $Z$ line to modulate effective qubit-qubit coupling $g_{eff}$. Theoretical modeling shows how the DTC cancels $g_{eff}$ contributions when $\\omega_m \\approx \\omega_p$, enabling robust, low-overhead control; experimentally, five qubits demonstrate suppressed $ZZ$ crosstalk, high-fidelity CZ gates, and strong entanglement generation (Bell states with fidelity $>$99.3% and a three-qubit GHZ with $96.0%$). A scalable parametric gate framework, including a parametric iSWAP with fidelity $96.7%$, and proposed 2D lattice layouts suggest the approach is compatible with surface-code architectures and scalable multiplexing. Collectively, the results indicate substantial reductions in wiring overhead and a viable path to large-scale, multiplexed superconducting quantum processors.

Abstract

Precise control of superconducting qubits is essential for advancing both quantum simulation and quantum error correction. Recently, transmon qubit systems employing the single-transmon coupler (STC) scheme have demonstrated high-fidelity single- and two-qubit gate operations by dynamically tuning the effective coupling between qubits. However, the integration of STCs increases the number of control lines, thereby posing a significant bottleneck for chip routing and scalability. To address this challenge, we propose a robust control line multiplexing scheme based on a double-transmon coupler (DTC) architecture, which enables shared coupler control lines to substantially reduce wiring complexity. Moreover, we experimentally verify that this multiplexed configuration efficiently suppresses undesirable static $ZZ$ coupling while maintaining accurate control over two-qubit gate operations. We further demonstrate the feasibility of the architecture through two distinct gate implementations: a fast coupler $Z$-control-based CZ gate and a parametric iSWAP gate. To validate the practical applicability of this multiplexing approach in quantum circuits, we prepare Bell and three-qubit GHZ states using the proposed scheme with fidelity exceeding 99% and 96%, respectively. This multiplexed DTC architecture offers significant potential to minimize wiring overhead in two-dimensional qubit arrays, thereby greatly enhancing the scalability of superconducting quantum processors.

Figures (5)

• Figure 1: The multiplexed DTC scheme. (a) Schematic diagram of a basic unit in the multiplexed DTC scheme, where three transmon qubits are coupled via two DTCs. The effective coupling strengths between qubits $Q_1$-$Q_2$ and $Q_2$-$Q_3$ are mediated by adjacent DTCs, which share a common $Z$ control line split into two branches on the chip. (b) Simplified circuit model corresponding to (a). Each DTC is represented as an integration of a fixed-frequency transmon qubit and a capacitively-shunted flux qubit (CSFQ) li2024realization. (c) Comparison of $ZZ$ coupling strengths in STC and DTC configurations. Based on our experimental circuit parameters, the STC exhibits significant variation in $ZZ$ coupling strength as a function of qubit detuning, whereas the DTC maintains a relatively stable $ZZ$ coupling. Moreover, the regime in which the $ZZ$ coupling remains below 10 kHz for the STC configuration is confined to a narrow crossing region, while the DTC sustains this low $ZZ$ coupling over a substantially broader range. This extended suppression window facilitates the practical implementation of control-line multiplexing within DTC architectures.
• Figure 2: Chip configuration and $ZZ$ coupling. (a) Optical micrograph of the superconducting quantum processor featuring five transmon qubits arranged in a one-dimensional chain architecture. The rightmost three qubits, $Q_i \ (i=1 \sim 3)$, are utilized to demonstrate the fundamental multiplexed unit, wherein the two DTCs coupling each qubit pair share a common $Z$ control line. (b) Enlarged views of the DTC and the multiplexed control lines. (c) Variation of $ZZ$ coupling as a function of qubit detuning and DTC $Z$ bias. Here, the frequency of $Q_2$ is held constant while the frequencies of $Q_3$ and the corresponding DTC are varied. The $ZZ$ suppression point shows negligible dependence on qubit detuning. (d) Idle frequency configuration of the three qubits $Q_i \ (i=1 \sim 3)$. The frequency detuning between $Q_1$-$Q_2$ is set within the straddling regime, whereas the detuning between $Q_2$-$Q_3$ lies outside this regime. (e) $ZZ$ coupling as a function of DTC $Z$ bias at the idle frequency configuration. The gray shaded region highlights the $Z$ bias range over which both qubit pairs maintain $ZZ$ coupling strengths below 100 kHz. (f) Comparison of gate fidelities obtained from simultaneous and isolated RB for qubits $Q_1$, $Q_2$ and $Q_3$. The consistent fidelities across simultaneous RB [$Q_1$: 99.91(1)%; $Q_2$: 99.90(1)%; $Q_3$: 99.86(1)%] and isolated RB [$Q_1$: 99.92(2)%; $Q_2$: 99.90(1)%; $Q_3$: 99.87(1)%] confirm effective suppression of $ZZ$ crosstalk within the multiplexed DTC scheme.
• Figure 3: CZ gate and spectator qubit effects. (a) Schematic diagram illustrating the investigation of the CZ gate and spectator qubit effects. After initializing all qubits in the $\ket{0}$ state, the spectator qubit is prepared in different states using the $I$, $X$ and $X/2$ operations to assess its impact on the error rate of the target CZ gate. (b) Pulse sequence for RB experiments. Following the application of drive pulses to the spectator qubit, the RB protocol is executed on the target qubit pair, which is subsequently measured. (c) CZ gate fidelities extracted from RB experiments. The left panel shows results with $Q_3$ as the spectator qubit, while the right panel corresponds to $Q_1$ as the spectator qubit. The top, middle, and bottom rows represent the outcomes when applying the $I$, $X$ and $X/2$ gates to the spectator qubit, respectively. The extracted CZ gate fidelities are 99.08%, 99.16%, and 99.15% (left panel), and 99.21%, 99.08%, and 99.00% (right panel). (d) QST density matrices for Bell states prepared on qubit pairs $Q_1$-$Q_2$ and $Q_2$-$Q_3$, achieving fidelities of 99.34% and 99.57%, respectively.
• Figure 4: Generation of three-qubit GHZ state. (a) Pulse sequence employed for the generation of three-qubit GHZ state. Here, $Z(\phi)$ denotes the virtual $Z$ gate used for phase compensation. (b) Phase calibration protocol for measuring single-qubit $Z$ phase shifts. The right panel illustrates the schematic of the Ramsey-type experiment designed to quantify the phase accumulated in the spectator qubit during CZ gate operations applied to the target qubit pair. The left panel presents the corresponding experimental data along with fitted curves, from which the phase offset is extracted. (c) QST density matrix of the generated three-qubit GHZ state, demonstrating a measured fidelity of 96.0%.
• Figure 5: Realization of the parametric iSWAP gate. (a) Conceptual schematic of the parametric iSWAP gate implementation using the multiplexed DTC scheme. The effective coupling strength $g_\mathrm{eff}$ is modulated to oscillate through the application of a parametric flux pulse on the DTCs. (b) Characterization of the effective coupling strength via chevron patterns. The qubits are initially prepared in the $\ket{10}$ (or $\ket{01}$) state, followed by fine-tuning of the qubit frequencies to achieve resonance. (c) Experimentally measured process matrix $\chi_\mathrm{exp}$ obtained from QPT of the parametric iSWAP gate, demonstrating a gate fidelity of 96.7%. The left panel displays the real components, while the right panel shows the imaginary components. Solid black outlines correspond to the ideal gate. (d) Two potential approaches for implementing control line multiplexing within a two-dimensional square-lattice qubit architecture. The left panel depicts a central qubit whose four adjacent couplers are controlled via a single shared line, whereas the right panel illustrates multiplexing of control lines along each row.