A Compact Model for Polar Multiple-Channel Field Effect Transistors: A Case Study in III-V Nitride Semiconductors
Aias Asteris, Thai-Son Nguyen, Huili Grace Xing, Debdeep Jena
TL;DR
This work addresses the challenge of efficiently predicting mobile carrier densities in polar multi-channel nitride heterostructures by deriving closed-form, analytically tractable expressions that couple electrostatics with quantum confinement. It extends a single-channel model to a multi-channel stack via periodic boundary conditions and augments it with intentional doping schemes (delta-doping and modulation-doping) to control 2DEG/2DHG populations, yielding total densities $n_s^{tot}$ and $p_s^{tot}$ and channel-threshold voltages $V_T^{pc}$ and $V_T^{tc}$. Validation against Schrödinger–Poisson simulations for various III-N configurations (AlGaN/GaN, AlInN/GaN, AlScN/GaN) shows good agreement and demonstrates how doping can reduce epitaxial thickness while maintaining carrier densities. The framework offers a fast, physically transparent design tool for next-generation nitride MC-FETs and establishes a foundation for incorporating source/drain/gate effects in future work.
Abstract
A compact analytical model is developed for the mobile charge density of polar multiple channel field effect transistors. Two dimensional electron and hole gases can be potentially induced by spontaneous and piezoelectric polarization in polar heterostructures. Focusing on the active region of devices that employ a multiple quantum-well layout, the total electron and hole populations are estimated from fundamental electrostatic and quantum mechanical principles. Hole gas depletion techniques, revolving around intentional donor doping, are modeled and evaluated, culminating in a generalized closed-form equation for the mobile carrier density across the doping schemes examined. The utility of this model is illustrated for the III-Nitride material system, exploring AlGaN/GaN, AlInN/GaN and AlScN/GaN heterostructures. The compact framework provided herein considerably elucidates and enhances the efficiency of multi-layered transistor design.
