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Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim

Wajid Ali, Ayaz Akram, Deepak Shankar

TL;DR

This work addresses the challenge of scaling performance in semiconductor design as Moore's Law slows by evaluating chiplet-based multi-die SoCs using VisualSim Architect. It systematically contrasts monolithic and chiplet architectures with varying memory configurations, core counts, and interconnects (UCIe and CMN600), measuring latency and power to assess scalability. The study finds that chiplet-based designs with dedicated DRAM and high-performance interconnects achieve better scalability and performance at the expense of higher power and some additional inter-chiplet latency, providing actionable guidance for future chiplet implementations. The results offer practical insights for designers aiming to optimize memory hierarchy, interconnect topology, and core distribution to meet growing workloads in chiplet-based systems.

Abstract

This paper focuses on the simulation of multi-die System-on-Chip (SoC) architectures using VisualSim, emphasizing chiplet-based system modeling and performance analysis. Chiplet technology presents a promising alternative to traditional monolithic chips, which face increasing challenges in manufacturing costs, power efficiency, and performance scaling. By integrating multiple small modular silicon units into a single package, chiplet-based architectures offer greater flexibility and scalability at a lower overall cost. In this study, we developed a detailed simulation model of a chiplet-based system, incorporating multicore ARM processor clusters interconnected through a ARM CMN600 network-on-chip (NoC) for efficient communication [4], [7]. The simulation framework in VisualSim enables the evaluation of critical system metrics, including inter-chiplet communication latency, memory access efficiency, workload distribution, and the power-performance tradeoff under various workloads. Through simulation-driven insights, this research highlights key factors influencing chiplet system performance and provides a foundation for optimizing future chiplet-based semiconductor designs.

Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim

TL;DR

This work addresses the challenge of scaling performance in semiconductor design as Moore's Law slows by evaluating chiplet-based multi-die SoCs using VisualSim Architect. It systematically contrasts monolithic and chiplet architectures with varying memory configurations, core counts, and interconnects (UCIe and CMN600), measuring latency and power to assess scalability. The study finds that chiplet-based designs with dedicated DRAM and high-performance interconnects achieve better scalability and performance at the expense of higher power and some additional inter-chiplet latency, providing actionable guidance for future chiplet implementations. The results offer practical insights for designers aiming to optimize memory hierarchy, interconnect topology, and core distribution to meet growing workloads in chiplet-based systems.

Abstract

This paper focuses on the simulation of multi-die System-on-Chip (SoC) architectures using VisualSim, emphasizing chiplet-based system modeling and performance analysis. Chiplet technology presents a promising alternative to traditional monolithic chips, which face increasing challenges in manufacturing costs, power efficiency, and performance scaling. By integrating multiple small modular silicon units into a single package, chiplet-based architectures offer greater flexibility and scalability at a lower overall cost. In this study, we developed a detailed simulation model of a chiplet-based system, incorporating multicore ARM processor clusters interconnected through a ARM CMN600 network-on-chip (NoC) for efficient communication [4], [7]. The simulation framework in VisualSim enables the evaluation of critical system metrics, including inter-chiplet communication latency, memory access efficiency, workload distribution, and the power-performance tradeoff under various workloads. Through simulation-driven insights, this research highlights key factors influencing chiplet system performance and provides a foundation for optimizing future chiplet-based semiconductor designs.

Paper Structure

This paper contains 8 sections, 11 figures.

Table of Contents

  1. Introduction
  2. Methodology
  3. Experimental Setup
  4. Simulation Framework
  5. Results and Discussions
  6. Behavioral Latency
  7. Power
  8. Conclusion

Figures (11)

  • Figure 1: Block diagram of Experiment 1: Monolithic SoC
  • Figure 2: Block diagram of Experiment 2: Chiplet-Based SoC.
  • Figure 3: Block diagram of Experiment 3: Multi-Chiplet SoC.
  • Figure 4: Behavioral Latency: Task Completion Time by CPU Clusters Experiment 1
  • Figure 5: Behavioral Latency: Task Completion Time by CPU Clusters Experiment 2
  • ...and 6 more figures