Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

TL;DR

The paper tackles the VT control problem in amorphous oxide semiconductor FETs for BEOL and 3D memory by using an ultrathin SiOx interfacial layer (SiL) to create a positive interfacial dipole. The authors deposit SiL via PEALD at 200 °C with no anneal, achieving a positive VT shift up to $0.50$ V while preserving mobility and subthreshold slope. They show a work-function increase for SiOx/IWO stacks and a predicted ~0.40 V dipole-induced band-edge shift; PBTI reliability is improved. In a 2T GC memory, SiL reduces the V_SN drop by ~67%, and maintains retention up to $10^4$ s with leakage reduced by three orders of magnitude, enabling lower refresh energy. The approach is CMOS-compatible and scalable, offering a practical route for back-end compatible oxide-semiconductor transistors and high-density embedded 3D memory.

Abstract

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.

Figures (5)

• Figure 1: (a) Fabrication process flow of AOSFETs. Schematic illustration of (b) FET structure incorporating a SiOx dipole layer, (c) 2T GC, where the source of the WTR is connected to the gate of the RTR. (d) Circuit diagram of the corresponding n-n 2T GC highlighting the SN. (e) Top-view AFM image of IWO channel showing smooth surface of the film, revealing a relatively smooth surface (Rq$<450 \pm20$ pm). (f) Top view SEM image of the fabricated GC showing RWL, RBL, WWL and WBL. Source of the write transistor is connected to the gate of the read transistor through SN. (g) Cross-sectional TEM image of the FET structure. (h) EDS elemental mapping illustrating uniform distribution of Hf, Si, Ti, In, Pt, Ni, O, and Au across the device cross-section.
• Figure 2: (a) Transfer characteristics (ID-VGS) of the BL and SiL device, measured at VDS 1 V. Here L = 1 $\upmu$m and W = 10 $\upmu$m. SiL devices clearly exhibit a positive VT shift. (b) VT distributions for different devices, showing that SiL devices achieve a maximum VT increase of $\sim$ 500 mV compared to the BL. Here, VT was extracted using constant current method at 100 nA*Width/Length. (c) $\upmu$FE of different devices indicate that $\upmu$FE remains largely unaffected by the SiL integration. (d) SS values of BL and SiL devices are within acceptable variation range. (e) UPS spectra acquired under applied bias (-10 V) for HfO2/IWO and SiO2/IWO samples. Inset shows zoomed view of the secondary electron cut-off region. The SiO2/IWO exhibits a higher work-function (4.08 eV) than HfO2/IWO (3.87 eV). (f) Simulated energy band-diagram of SiL OSFET obtained using one dimensional (1D) Poisson solver. (g) A positive dipole forms at the SiO2/IWO interface. (h) Comparison of $\Delta \text{V}_{\text{T}}$=VT-VBL, for devices employing SiOx and an alternate interfacial dipole material (AlOx). Except at a dipole thickness of $0.6\,\mathrm{nm}$, where AlOx shows a slightly larger $\Delta \text{V}_{\text{T}}$, the SiOx cases exhibit higher $\Delta \text{V}_{\text{T}}$ as a function of thickness, most noticeably at the saturation point (by $\sim 50\,\mathrm{mV}$).
• Figure 3: Positive-bias temperature instability of AOSFETs with and without dipole layers, stress applied up to 1000 s at 85 $\degree$C under over-drive biases of 0.5 V, 1.0 V, and 2 V. The dashed lines represent the model fits. (a) BL devices show a negative VT shift of $\sim$$-$300 mV at 2 MV/cm, attributed to hydrogen release from the gate dielectric that creates donor-like defects. (b) Dipole-engineered SiL devices exhibit a positive VT shift of $\sim$150 mV, indicating that the SiOx interfacial layer shifts the dominant degradation mechanism to electron trapping. (c) Devices with an AlOx interfacial dipole layer show a smaller negative VT shift of around -43 mV at Vov of 2 V at 1000 s. Both SiOx and AlOx interfacial dipole layers eliminate the large negative VT shift observed in BL devices enabling improved reliability.
• Figure 4: Timing diagram for the BL and SiL GC memory. (a) Measured waveforms as a function of time: (i) WWL, WBL, and RWL voltages, (ii) IRBL, and (iii) storage-node voltage VSN. VSN decays in two stages: an immediate "fast" drop coincident with the falling edge of the WWL (red region), followed by a "slow" drop driven by post-write leakage (green region). (b) Distributions of the fast and slow components of VSN loss for BL and SiL GCs. SiL GCs show lower VSN drop compared to BL GCs. (c) Distribution of the total VSN drop. The fast component is governed by the write-transistor VT; the higher VT achieved with the SiOx interfacial layer suppresses mobile charge sharing from the WTR to the SN and WBL, reducing both fast and overall VSN drops relative to the BL.
• Figure 5: Retention performance of baseline and SiL GCs. (a) Bias condition during standby; WWL is held at $-0.5$ V. Here, RTR L = 3 $\upmu$m, W = 10 $\upmu$m, WTR L = 2 $\upmu$m, W = 10 $\upmu$m. (b) The SiOx-dipole GC SiL4 shows improved retention (up to 10 000 s) compared to BL GC. (c) State-1 retention for the BL and various SiL GCs, measured for 2 000 s; State-1 is reported because it is the critical state and typically degrades fastest. (d) Leakage current extracted from VSN degradation (defined as a 0.1 V drop from the initial value) for BL and SiL GCs. Leakage decreases exponentially with increasing VT in the SiL GCs, achieving a three-order-of-magnitude reduction in the SiL4 GCs.