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MOSAIX Qualification System for ALICE ITS3

Ola Groettvik

TL;DR

The paper addresses the challenge of qualifying a highly integrated wafer-scale MAPS sensor (MOSAIX) intended for ALICE ITS3, where 144 tiles and multiple high-speed links must function as a single system before production. It presents a unified qualification framework built around an Arria 10 FPGA-based test system and a dedicated MOSAIX emulator to enable day-one readiness. Key contributions include the hardware-software co-design of a multi-target test platform, a rigorous firmware verification strategy using UVM and CI, and an emulator that accelerates integration testing and training. The work reduces development risk, informs dicing and yield strategies, and is essential for meeting ITS3 deployment timelines.

Abstract

The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in high-energy physics. MOSAIX, a fully functional prototype and the final development step before production, measures 266 mm by 19 mm. The chip integrates 144 independently powered pixel matrices, eight 10 Gb/s transmitters, and on-chip power and data distribution. This contribution presents the development of the MOSAIX test system and verification strategy, with emphasis on validating the testing infrastructure before chip availability. The system includes an FPGA that controls MOSAIX and parses its output, and a second MOSAIX emulator FPGA.

MOSAIX Qualification System for ALICE ITS3

TL;DR

The paper addresses the challenge of qualifying a highly integrated wafer-scale MAPS sensor (MOSAIX) intended for ALICE ITS3, where 144 tiles and multiple high-speed links must function as a single system before production. It presents a unified qualification framework built around an Arria 10 FPGA-based test system and a dedicated MOSAIX emulator to enable day-one readiness. Key contributions include the hardware-software co-design of a multi-target test platform, a rigorous firmware verification strategy using UVM and CI, and an emulator that accelerates integration testing and training. The work reduces development risk, informs dicing and yield strategies, and is essential for meeting ITS3 deployment timelines.

Abstract

The ALICE Inner Tracking System upgrade (ITS3) will employ stitched, wafer-scale Monolithic Active Pixel Sensors (MAPS) for the first time in high-energy physics. MOSAIX, a fully functional prototype and the final development step before production, measures 266 mm by 19 mm. The chip integrates 144 independently powered pixel matrices, eight 10 Gb/s transmitters, and on-chip power and data distribution. This contribution presents the development of the MOSAIX test system and verification strategy, with emphasis on validating the testing infrastructure before chip availability. The system includes an FPGA that controls MOSAIX and parses its output, and a second MOSAIX emulator FPGA.

Paper Structure

This paper contains 9 sections, 3 figures.

Table of Contents

  1. Introduction
  2. The MOSAIX Sensor: A Qualification Challenge
  3. Qualification Strategy and System Architecture
  4. A Unified Test System
  5. Control and Software Architecture
  6. The MOSAIX Emulator
  7. Implementation
  8. Development and Impact
  9. Status and Conclusion

Figures (3)

  • Figure 1: A map of the major testing and characterization phases for MOSAIX. A substantial core of functionalities must be validated before pixel-level characterization can even begin, highlighting the system's high level of integration. ADC testing is a quasi-dependency for pixel matrix qualification, as it can be circumvented by using the external ADC path.
  • Figure 2: The MOSAIX carrier card is one of the targets for the qualification system. It allows for deeper characterization and observability compared to testing on the wafer prober, e.g. the measurement of the IR-drop along the long edge (z-axis) of the sensor.
  • Figure 3: Integration test setup for the MOSAIX segment carrier PCB.