Characterization of the H2M Monolithic CMOS Sensor

TL;DR

This study presents the H2M monolithic pixel sensor, a MAPS implemented in a modified 65 nm TPSCo process with a small collection electrode and a digital-on-top architecture. By combining laboratory and test-beam measurements with TCAD and Monte Carlo simulations, the authors characterize thresholds, timing, efficiency, and spatial performance across four readout modes and show that backside thinning to 21 µm preserves MIP detection efficiency above 99% at modest thresholds around 205 e⁻. The work identifies non-uniform in-pixel response due to local potential wells near the analog n-well as the dominant impairing factor, and demonstrates through simulations that optimized n-well layouts can greatly improve uniformity and overall efficiency (up to ~95%). The results validate the digital-on-top, per-pixel processing approach for MAPS in a large-pitch, thin sensor context, and provide a clear path for refining future devices. Overall, H2M confirms the viability of 65 nm MAPS with compact digital logic for high-efficiency, low-mass particle tracking applications.

Abstract

The H2M (Hybrid-to-Monolithic) is a monolithic pixel sensor manufactured in a modified \SI{65}{\nano\meter}~CMOS imaging process with a small collection electrode. Its design addresses the challenges of porting an existing hybrid pixel detector architecture into a monolithic chip, using a digital-on-top design methodology, and developing a compact digital cell library. Each square pixel integrates an analog front-end and digital pulse processing with an 8-bit counter within a \SI{35}{\micro\meter}~pitch. This contribution presents the performance of H2M based on laboratory and test beam measurements, including a comparison with analog front-end simulations in terms of gain and noise. A particular emphasis is placed on backside thinning in order to reduce material budget, down to a total chip thickness of \SI{21}{\micro\meter} for which no degradation in MIP detection performance is observed. For all investigated samples, a MIP detection efficiency above \SI{99}{\%} is achieved below a threshold of approximately 205 electrons. At this threshold, the fake-hit rate corresponds to a matrix occupancy of fewer than one pixel per the \SI{500}{\nano\second}~frame. Measurements reveal a non-uniform in-pixel response, attributed to the formation of local potential wells in regions with low electric field. A simulation flow combining technology computer-aided design, Monte Carlo, and circuit simulations is used to investigate and describe this behavior, and is applied to develop mitigation strategies for future chip submissions with similar features.

Figures (45)

• Figure 1: H2M cross section sketch of one pixel, with drift paths of electrons indicated by red arrows. The approximately 5µm metal interconnect layers are not shown in the schematic.
• Figure 2: Simplified layout of the n-well and p-well positions within the deep p-well in four pixels. The locations of the analog front-end and digital logic are shown. The collection electrode, placed outside the deep p-well, is also indicated. The pixel cell boundary is marked with a dashed red line.
• Figure 3: Schematic of the pixel analog front-end.
• Figure 4: Schematic layout of the four acquisition modes. On top, the CSA output signal is represented with a triangular shape, whose return-to-baseline slope depends on the ikrum setting. In the middle, for the high ikrum, the signal is compared to a reference voltage threshold, and the corresponding measured counts in ToT, ToA, and photon counting modes are indicated. At the bottom, a readout in triggered mode is depicted, using as an example, a configurable preset of 253 counts and a strobe duration of 2 clock cycles.
• Figure 5: Simulated amplitude response of the CSA as a function of the injected signal vtpulse, for three different ikrum settings.