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CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems

Lukas Pfromm, Alish Kanani, Harsh Sharma, Janardhan Rao Doppa, Partha Pratim Pande, Umit Y. Ogras

TL;DR

CHIPSIM addresses the challenge of accurately simulating deep neural networks on chiplet-based systems by introducing a time-synchronized co-simulation framework that jointly models computation and inter-chiplet communication, along with microsecond-resolution power and thermal analysis. The framework coordinates a Global Manager with modular backends (e.g., CiMLoop for IMC compute and HeteroGarnet for NoI traffic) and supports heterogeneous chiplets, arbitrary NoI topologies, and multi-model pipelined workloads. Key contributions include a comprehensive, open-source co-simulation platform, extensive evaluations showing up to 340% accuracy improvement over baselines, and integrated power/thermal analysis, plus hardware validation that matches measurements within a few percent. CHIPSIM thus enables rapid, accurate design-space exploration and performance/power/thermal optimization for next-generation chiplet-based AI accelerators.

Abstract

Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework's versatility, up to 340% accuracy improvement, and power/thermal analysis capability.

CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems

TL;DR

CHIPSIM addresses the challenge of accurately simulating deep neural networks on chiplet-based systems by introducing a time-synchronized co-simulation framework that jointly models computation and inter-chiplet communication, along with microsecond-resolution power and thermal analysis. The framework coordinates a Global Manager with modular backends (e.g., CiMLoop for IMC compute and HeteroGarnet for NoI traffic) and supports heterogeneous chiplets, arbitrary NoI topologies, and multi-model pipelined workloads. Key contributions include a comprehensive, open-source co-simulation platform, extensive evaluations showing up to 340% accuracy improvement over baselines, and integrated power/thermal analysis, plus hardware validation that matches measurements within a few percent. CHIPSIM thus enables rapid, accurate design-space exploration and performance/power/thermal optimization for next-generation chiplet-based AI accelerators.

Abstract

Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as rapidly growing deep neural network (DNN) models. Chiplet-based architectures offer a cost-effective and scalable solution by integrating smaller chiplets via a network-on-interposer (NoI). Fast and accurate simulation approaches are critical to unlocking this potential, but existing methods lack the required accuracy, speed, and flexibility. To address this need, this work presents CHIPSIM, a comprehensive co-simulation framework designed for parallel DNN execution on chiplet-based systems. CHIPSIM concurrently models computation and communication, accurately capturing network contention and pipelining effects that conventional simulators overlook. Furthermore, it profiles the chiplet and NoI power consumptions at microsecond granularity for precise transient thermal analysis. Extensive evaluations with homogeneous/heterogeneous chiplets and different NoI architectures demonstrate the framework's versatility, up to 340% accuracy improvement, and power/thermal analysis capability.

Paper Structure

This paper contains 25 sections, 11 figures, 8 tables.

Table of Contents

  1. Introduction
  2. Related Work
  3. CHIPSIM Chiplet Co-simulation Framework
  4. Overview of the Proposed Framework
  5. Input Workload and Mapping
  6. Compute Simulation
  7. Communication Simulation
  8. Co-simulation Coordination
  9. Concrete Methodology Implementation
  10. Computation Simulation
  11. Communication Simulation
  12. Power Analysis and Thermal Simulation
  13. Experimental Evaluations
  14. Experimental Setup
  15. Performance Comparisons vs Baseline Approaches
  16. ...and 10 more sections

Figures (11)

  • Figure 1: An illustration of the CHIPSIM framework on a non-mesh heterogeneous chiplet-based system.
  • Figure 2: A visual comparison between existing simulators and the proposed simulation methodology.
  • Figure 3: Outline of the proposed simulation framework.
  • Figure 4: An illustrative event diagram showing the interleaving of different simulation operations.
  • Figure 5: The illustration of our concrete implementation and interface with thermal simulations.
  • ...and 6 more figures