Reconfigurable Analog Computers
Bernd Ulmann
TL;DR
The paper surveys the evolution of reconfigurable analog computers, focusing on autopatch concepts from mechanical interconnects to hierarchical switch matrices. It analyzes voltage vs current coupling and how mixed interconnect schemes (e.g., LUCIDAC/REDAC) enable scalable, sparse configurations and efficient coefficient handling. Key contributions include a historical perspective on patching architectures (Rockefeller, Hannauer, SIMSTAR), design principles for coefficients and DAC implementations, and a discussion of configuration-time challenges with a push toward sparse updates. The work highlights the potential of analog co-processors for HPC due to energy efficiency and fast solution times, while emphasizing the need for software tooling to integrate these systems into modern workflows.
Abstract
The Achilles heel of classic analog computers was the complex, error prone, and time consuming process of programming. This typically involved manually patching hundreds or even thousands of connections between individual computing elements as well as setting many precision 10-turn potentiometers manually, often taking hours, or even days. Albeit being simplified by means of removable patch panels, switching from one program to another still was time consuming and thus expensive. With digital computers about to hit physical boundaries with respect to energy consumption, clock frequency, and integration density, analog computers have gained a lot of interest as co-processors for certain application areas in recent years. This requires some means for automatic reconfiguration of these systems under control of an attached digital computer. The following sections give an overview of classic and modern approaches towards such autopatch systems.