Improved operating voltage in InGaN-capped AlGaN-based DUV LEDs on bulk AlN substrates

Abstract

Better wall plug efficiency of deep-ultraviolet light emitting diodes (DUV-LEDs) requires simultaneous low resistivity p-type and n-type contacts, which is a challenging problem. In this study, the co-optimization of p-InGaN and n- AlGaN contacts for DUV LEDs are investigated. We find that using a thin 7%InGaN cap is effective in achieving ohmic p-contacts with specific contact resistivity of 3.10x10^{-5} Ohm.cm^2. Upon monolithic integration of p- and n- contacts for DUV LEDs, we find that the high temperature annealing of 800C required for the formation of low resistance contacts to n-AlGaN severely degrades the p-InGaN layer, thereby reducing the hole concentration and increasing the specific contact resistivity to 9.72x10^{-4} Ohm.cm^2. Depositing a SiO2 cap by plasma-enhanced atomic layer deposition (PE-ALD) prior to high temperature n-contact annealing restores the low p-contact resistivity, enabling simultaneous low-resistance p- and n-contacts. DUV-LEDs emitting at 268 nm fabricated with the SiO2 capping technique exhibit a 3.5 V reduction in operating voltage at a current level of 400 A/cm^2 and a decrease in differential ON-resistance from 6.4 mOhm.cm^2 to 4.5 mOhm.cm^2. This study highlights a scalable route to high-performance, high-Al-content bipolar AlGaN devices.

Figures (5)

• Figure 1: (a) Schematic of the p-GaN contact samples without (sample A) and with (sample B) a p-InGaN cap. (b) CTLM-IV curves from the two samples. (c) Specific contact resistivity vs current level for the data shown in (b). The contact resistance of sample B is $R$$_{\mathrm{c}}$ = 8.4 $\Omega$mm. (d)-(e) Energy band diagram simulations of sample A and sample B, respectively.
• Figure 2: (a) Heterostructure of the DUV LED samples used for this contact annealing temperature-dependent study. (b) Specific contact resistivity of n- and p-contact vs n-contact annealing temperature. P-contacts were subsequently annealed at 450 $^{\circ}$C. All resistance values were extracted at 1 mA from CTLM-IV measurement. (c) Sheet resistance vs n-contact annealing temperature.
• Figure 3: Schematic diagram illustrating the fabrication process of an LED with the SiO$_{2}$ capping technique. (a) Expitaxial growth. (b) Mesa formation by ICP-RIE. (c) Deposition of SiO$_{2}$ by ALD. (d) Deposition and annealing of n-type metal contacts (e) Deposition and annealing of p-type metal contacts.
• Figure 4: (a) CTLM-IV curves comparison of p-contact without undergoing n contact anneal, after undergoing n-contact anneal with SiO$_{2}$ cap, and after undergoing n-contact anneal without SiO$_{2}$ cap. IVs are plotted for 2 µ m spacing. (b) Specific contact resistivity vs current level for the data shown in (a).
• Figure 5: (a) Room temperature J-V characteristics of two LEDs, one with SiO$_{2}$ capping method and one without. The differential ON-resistance was extracted at 400 A/cm$^2$. (b) IV from batch test of LEDs with and without SiO$_{2}$ capping. (c) Room temperature electroluminescence of an LED with the SiO$_{2}$ capping method. Inset shows the microscopy image of a fabricated LED.