2D Canonical Approach for Beating the Boltzmann Tyranny Using Memory

Abstract

The 60 mV$/$decade subthreshold limit at room temperature, coined as the Boltzmann tyranny, remains a fundamental obstacle to the continued down-scaling of conventional transistors. While several strategies have sought to overcome this constraint through non-thermal carrier injection, most rely on ferroelectric-based or otherwise material-specific mechanisms that require complex fabrication and stability control. Here, we develop a universal theoretical framework showing that intrinsic memory effects in nanometric field-effect transistors can naturally bypass this limit. Within the Landauer-Büttiker quantum transport formalism, we incorporate charge-trapping mechanisms that dynamically renormalize the conduction band edge. The resulting analytical expression for the subthreshold swing explicitly links memory dynamics to gate efficiency, revealing that a reduced carrier generation rate or enhanced trapping activity leads to sub-thermal switching, thus breaking the Boltzmann barrier. The model captures key experimental features and provides clear, generalizable design principles, establishing memory-assisted transistors as a robust pathway toward ultra-low-power and multifunctional electronic architectures.

Figures (2)

• Figure 1: Baseline characteristics of a 2D diffusive nanotransistor under the near-equilibrium transport approximation. (a) Schematic of the modeled 2D diffusive field-effect transistor, showing a channel of length $L$ and width $W$, source/drain contacts, and a gate applying voltage $V_g$. (b) Energy diagram illustrating the principle of thermalization-driven current. An applied bias $V_{ds}$ creates an energy difference between the chemical potentials of the source ($\mu - eV_{ds}$) and drain ($\mu$), opening a Fermi conduction window that enables net current flow. (c) Calculated output characteristics: current versus bias voltage ($\eta_{ds} V_{ds}$) for various fixed gate voltages ($\eta_g V_g$). (d) Calculated transfer characteristic: current versus $\eta_g V_g$ for several fixed bias voltages. (e) Current response in the linear regime (low $V_{ds}$), at $V_{g} \rightarrow \infty$. (f) Saturation current as a function of $\eta_g V_g$ in the high-bias limit ($V_{ds} \rightarrow \infty$), revealing two contrasting approximately linear trends at small $V_g$ (solid red line) and large $V_g$ (dashed line). All calculations were performed at $T = 300~\mathrm{K}$.
• Figure 2: Memory-induced phenomena and sub-thermal switching. (a) Calculated $I$--$V$ curve under a triangular voltage sweep (inset), showing the hysteresis loop characteristic of memory effects. (b) Gate-voltage-dependent charge generation functions $g(V_g)$ that determine the memory dynamics. (c) Corresponding transfer characteristics [lg$(I)$ vs $V_g$], highlighting how memory modifies the subthreshold turn-on compared to the memory-less case (dashed line). (d) Subthreshold Swing (SS) as a function of $V_g$, showing that for $\mathrm{d}g/\mathrm{d}V_g < 0$ (blue curves), the model predicts sub-thermal switching with SS well below the 60 mV/decade Boltzmann limit (gray dashed line).