Architecting Scalable Trapped Ion Quantum Computers using Surface Codes

TL;DR

This work addresses scaling trapped-ion quantum computers by integrating surface-code QEC with QCCD hardware. It develops a topology-aware QEC-to-QCCD compiler that maps surface-code parity checks to native QCCD primitives, clusters data qubits into trap-sized groups, routes ions under strict hardware constraints, and schedules operations; Stim is used to estimate logical error rates under a realistic noise model, including vibrational effects. The key finding is that using small traps with capacity $2$, a grid topology, and direct wiring achieves near-optimal QEC round times and low logical error rates, outperforming existing compilers by roughly a factor of $3.8$ in logical clock speed, while revealing substantial power and data-rate challenges in current wiring schemes. The results underscore a power–cycle-time trade-off in control architectures (standard vs. WISE wiring) and advocate hardware–software co-design to scale surface-code QEC on TI QCCD systems toward hundreds of logical qubits with target logical error rates around $10^{-9}$. These insights provide concrete guidance for designing scalable, fault-tolerant trapped-ion quantum computers by balancing architectural choices, wiring, and compiler capabilities.

Abstract

Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems ($10^{-3}$ to $10^{-4}$) and the requirements of practical applications (below $10^{-9}$). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.

Figures (13)

• Figure 1: Quantum Charge-Coupled Device (QCCD) system. A detailed view of the QCCD hardware, where ions (grey circles) serve as qubits and are confined within an electromagnetic field known as a trap. (a) The trap is structured with different types of electrodes to position ions, including dynamic electrodes (green) for time-varying signals and shim electrodes (blue) for static potentials. Transport segments (black) and junctions (orange) allow ions to move between traps. (b) The QCCD device is controlled by a classical system interfacing with Digital-to-Analog Converters (DACs), each responsible for individual electrode voltages, enabling precise ion control Lekitsch_2017. (c) We use an abstract QCCD view for this paper.
• Figure 2: Framework for evaluating the suitability of a candidate QCCD-based TI system for error correction. Taking a candidate architecture and a candidate QEC code as input, the tool flow computes error correction metrics such as logical error rate, QEC round time and power dissipation requirements by using a QEC and device topology-aware compiler, QCCD simulator, and realistic models for performance and resource estimation.
• Figure 3: The topology of the distance four surface code. The blue circles represent physical data qubits, and the red circles represent physical ancilla qubits. Data qubits form the vertices of the cells that make up the shaded surface, and there is exactly one ancilla qubit in the centre of every cell. The cells are shaded purple or green to disambiguate the two types of parity checks, with each type of circuit given on the right.
• Figure 4: (a) Each electrode is connected to a dedicated DAC in the standard architecture, resulting in a direct but highly resource-intensive wiring scheme. (b) The WISE architecture integrates an ion trap with a switch-based demultiplexing network, significantly altering the scaling of control electronics. All dynamic electrodes (green) are controlled with $\approx 100$ DACs irrespective of system size by using a switch network, but this comes at the cost that only primitive QCCD operations of the same type (t1-t11 §\ref{['def:QCCD_toolbox']}) can execute simultaneously. One DAC can set $\approx 100$ shim electrodes (blue).
• Figure 5: QCCD compilation flow: from a distance 2 surface code (syndrome extraction) circuit (top-left) and QCCD device configuration (top-right) to a scheduled, executable QCCD program. Steps include translation to native gates, qubit-to-ion mapping, ion routing using the movement primitives from the QCCD toolbox (§\ref{['subsecTopoCodesBackground']}), and scheduling using the operation timings in Table \ref{['tab:operations']}.