Towards a Functionally Complete and Parameterizable TFHE Processor
Valentin Reyes Häusler, Gabriel Ott, Aruna Jayasena, Andreas Peter
TL;DR
The paper tackles the latency and bandwidth bottlenecks of fully homomorphic encryption by proposing a fully FPGA based TFHE processor that executes programmable bootstrapping and related TFHE operations entirely on-chip. The authors design a compact, scalable architecture featuring optimized modular reduction, an NTT based negacyclic multiplier, external product, blind rotation, PBS, and a dual purpose key switching module. Experimental results demonstrate substantial PBS throughput gains relative to prior FPGA implementations, along with favorable resource usage and energy efficiency across standard and large parameter sets. This integrated approach promises practical privacy preserving computation and establishes a foundation for future TFHE processor architectures and ASIC implementations.
Abstract
Fully homomorphic encryption allows the evaluation of arbitrary functions on encrypted data. It can be leveraged to secure outsourced and multiparty computation. TFHE is a fast torus-based fully homomorphic encryption scheme that allows both linear operations, as well as the evaluation of arbitrary non-linear functions. It currently provides the fastest bootstrapping operation performance of any other FHE scheme. Despite its fast performance, TFHE suffers from a considerably higher computational overhead for the evaluation of homomorphic circuits. Computations in the encrypted domain are orders of magnitude slower than their unencrypted equivalents. This bottleneck hinders the widespread adoption of (T)FHE for the protection of sensitive data. While state-of-the-art implementations focused on accelerating and outsourcing single operations, their scalability and practicality are constrained by high memory bandwidth costs. In order to overcome this, we propose an FPGA-based hardware accelerator for the evaluation of homomorphic circuits. Specifically, we design a functionally complete TFHE processor for FPGA hardware capable of processing instructions on the data completely on the FPGA. In order to achieve a higher throughput from our TFHE processor, we implement an improved programmable bootstrapping module, which outperforms the current state-of-the-art by 240% to 480% more bootstrappings per second. Our efficient, compact, and scalable design lays the foundation for implementing complete FPGA-based TFHE processor architectures.