Enabling Vibration-Based Gesture Recognition on Everyday Furniture via Energy-Efficient FPGA Implementation of 1D Convolutional Networks

TL;DR

This work tackles the challenge of real-time, energy-efficient vibration-based gesture recognition on everyday furniture by removing costly spectral preprocessing and deploying compact 1D convolutional networks on a low-power FPGA. It introduces two architectures, 1D-CNN and 1D-SepCNN, with drastically reduced parameter counts (as few as 216 for 1D-SepCNN) and uses integer-only quantization plus RTL generation to enable FPGA deployment, complemented by a ping-pong buffering scheme for memory efficiency. A hardware-aware Optuna-based search optimizes configurations under accuracy, latency, and energy constraints, achieving sub-10 ms latencies and sub-1.2 mJ per inference on an AMD Spartan-7 FPGA, with PS accuracy up to 0.970 and LOSO performance demonstrating competitive generalization. The results show practical viability for edge deployment, enabling responsive, privacy-preserving smart furniture interfaces and informing future work on broader gestures and online real-time use.

Abstract

The growing demand for smart home interfaces has increased interest in non-intrusive sensing methods like vibration-based gesture recognition. While prior studies demonstrated feasibility, they often rely on complex preprocessing and large Neural Networks (NNs) requiring costly high-performance hardware, resulting in high energy usage and limited real-world deployability. This study proposes an energy-efficient solution deploying compact NNs on low-power Field-Programmable Gate Arrays (FPGAs) to enable real-time gesture recognition with competitive accuracy. We adopt a series of optimizations: (1) We replace complex spectral preprocessing with raw waveform input, eliminating complex on-board preprocessing while reducing input size by 21x without sacrificing accuracy. (2) We design two lightweight architectures (1D-CNN and 1D-SepCNN) tailored for embedded FPGAs, reducing parameters from 369 million to as few as 216 while maintaining comparable accuracy. (3) With integer-only quantization and automated RTL generation, we achieve seamless FPGA deployment. A ping-pong buffering mechanism in 1D-SepCNN further improves deployability under tight memory constraints. (4) We extend a hardware-aware search framework to support constraint-driven model configuration selection, considering accuracy, deployability, latency, and energy consumption. Evaluated on two swipe-direction datasets with multiple users and ordinary tables, our approach achieves low-latency, energy-efficient inference on the AMD Spartan-7 XC7S25 FPGA. Under the PS data splitting setting, the selected 6-bit 1D-CNN reaches 0.970 average accuracy across users with 9.22 ms latency. The chosen 8-bit 1D-SepCNN further reduces latency to 6.83 ms (over 53x CPU speedup) with slightly lower accuracy (0.949). Both consume under 1.2 mJ per inference, demonstrating suitability for long-term edge operation.

Figures (8)

• Figure 1: Illustration of Vibration-Sensing Setup for Swipe Recognition on an Ordinary Table Mounted by Four Sensors
• Figure 2: Schematic diagram of an 1D-CNN accelerator
• Figure 3: Selected model configurations with best integer-only test accuracy on person A of DataByPerson dataset.
• Figure 4: Overview of the deployment workflow, modified from ling2025deployment
• Figure 5: Confusion matrices of 1D-SepCNN models from Table \ref{['tab:exp2']} across data splitting methods.