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Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications

L. Hemanth Krishna, Srinivasu Bodapati, Sreehari Veeramachaneni, BhaskaraRao Jammu, Noor Mahammad Sk

TL;DR

The paper tackles the challenge of energy-efficient signed multiplication for edge-detection tasks by introducing sign-focused compressors, including exact designs A+B+C+1 and A+B+C+D+1, and corresponding approximate variants. It employs a truncation strategy on the lower N−1 partial-product columns coupled with an error-compensation mechanism to balance accuracy and hardware efficiency, implemented within an N×N signed multiplier using a three-region (LSP/CSP/MSP) architecture and a final CSA. The approach achieves a notable $29.21 ext{%}$ reduction in power-delay product and a $14.39 ext{%}$ reduction in power over the best existing multipliers while preserving edge features in a convolution-based edge-detection task, evidenced by a PSNR of $20.13$ dB relative to the exact multiplier. Overall, the work demonstrates practical applicability in real-world image processing pipelines and offers a scalable path to low-power, high-performance edge-detection accelerators.

Abstract

This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications.

Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications

TL;DR

The paper tackles the challenge of energy-efficient signed multiplication for edge-detection tasks by introducing sign-focused compressors, including exact designs A+B+C+1 and A+B+C+D+1, and corresponding approximate variants. It employs a truncation strategy on the lower N−1 partial-product columns coupled with an error-compensation mechanism to balance accuracy and hardware efficiency, implemented within an N×N signed multiplier using a three-region (LSP/CSP/MSP) architecture and a final CSA. The approach achieves a notable reduction in power-delay product and a reduction in power over the best existing multipliers while preserving edge features in a convolution-based edge-detection task, evidenced by a PSNR of dB relative to the exact multiplier. Overall, the work demonstrates practical applicability in real-world image processing pipelines and offers a scalable path to low-power, high-performance edge-detection accelerators.

Abstract

This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications.
Paper Structure (12 sections, 8 equations, 10 figures, 5 tables)

This paper contains 12 sections, 8 equations, 10 figures, 5 tables.

Table of Contents

  1. Introduction
  2. Implementation of Signed Multiplication Using Baugh-Wooley Algorithm
  3. Existing Signed Exact Compressors
  4. Proposed Compressor-Based Approximate Signed Multiplier Design
  5. Proposed Sign-Focus Compressors
  6. Approximate Signed Multiplier Architecture
  7. Error Compensation
  8. Application: Convolution-Based Edge Detection Using the Proposed Multiplier
  9. Results and Discussion
  10. Error Analysis
  11. Hardware Analysis
  12. Conclusion

Figures (10)

  • Figure 1: Baugh-Wooley algorithm for signed $8 \times 8$ multiplication baugh1974.
  • Figure 2: Schematic comparison of compressor (a) Exact Compressor Du2022 (b) Approximate compressor Esposito2018 (c) Approximate compressor Guo2019 (d) Approximate compressor Strollo2020 (e) Approximate compressor Akbari2017 (f) Approximate compressor Laimin.
  • Figure 3: Proposed exact sign-focus compressors: (a) $A + B + C + 1$, (b) $A + B + C + D + 1$
  • Figure 4: Proposed approximate sign-focus compressor designs: (a) $A + B + C + 1$, (b) $A + B + C + D + 1$
  • Figure 5: Partial product column partitioning in the proposed approximate signed multiplier architecture
  • ...and 5 more figures