RejSCore: Rejection Sampling Core for Multivariate-based Public key Cryptography

TL;DR

Post-quantum MPKC, exemplified by QR-UOV, relies on rejection sampling, which burdens hardware resources in constrained devices. The authors introduce RejSCore, a coprocessor-style accelerator combining an AES-CTR-128 based PRNG with a lightweight iterative rejection sampling unit, specifically targeted at QR-UOV with NIST SL-I parameters $($ $q=127$, $v=156$, $m=54$, $l=3$ $)$, and designed for modular extension to higher security levels. The architecture features a 26-bit instruction format, a dual-port memory, and an AES-CTR wrapper that yields a 21-cycle latency from seed to random output, achieving 222 MHz on Artix-7 FPGA and 565 MHz on 65 nm ASIC with favorable ADP and PDP. Experimental results show total operation in 8525 cycles, with detailed breakdowns for the RejSamp and AES components, demonstrating suitability for embedded PQC accelerators and paving the way for SHAKE-based PRNG variants and broader level support in future work.

Abstract

Post-quantum multivariate public key cryptography (MPKC) schemes resist quantum threats but require heavy operations, such as rejection sampling, which challenge resource-limited devices. Prior hardware designs have addressed various aspects of MPKC signature generation. However, rejection sampling remains largely unexplored in such contexts. This paper presents RejSCore, a lightweight hardware accelerator for rejection sampling in post-quantum cryptography. It specifically targets the QR-UOV scheme, which is a prominent candidate under the second-round of the National Institute of Standards and Technology (NIST) additional digital signature standardization process. The architecture includes an AES-CTR-128-based pseudorandom number generator. Moreover, a lightweight iterative method is employed in rejection sampling, offering reduced resource consumption and area overhead while slightly increasing latency. The performance of RejSCore is comprehensively evaluated on Artix-7 FPGAs and 65 nm CMOS technology using the Area-Delay Product (ADP) and Power-Delay Product (PDP). On Artix-7 and 65 nm CMOS, RejSCore achieves an area of 2042 slices and 464,866~$μm^2$, with operating frequencies of 222 MHz and 565 MHz, respectively. Using the QR-UOV parameters for security level I ($q = 127$, $v = 156$, $m = 54$, $l = 3$), the core completes its operation in 8525 clock cycles. The ADP and PDP evaluations confirm RejSCore's suitability for deployment in resource-constrained and security-critical environments.

Figures (1)

• Figure 1: RejSCore: Lightweight rejection sampling core for QR-UOV using AES-CTR-based PRNG.