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RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN

Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma

TL;DR

RAMAN tackles the challenge of resource-constrained edge AI by introducing a resource-efficient approximate $Posit(8,2)$ MAC (REAP) and a scalable Vector Execution Unit. Through an algorithm-hardware co-design framework with approximation-aware training, RAMAN balances hardware efficiency with application accuracy, demonstrated on FPGA and ASIC with substantial resource savings and strong MNIST accuracy. Key contributions include the REAP MAC, a modular VEU that enables reuse across diverse workloads, and a quantization-aware training workflow validated via Tiny-YOLOv3. This work offers a practical path toward high-density, energy-efficient edge accelerators that maintain robust learning performance under hardware approximation.

Abstract

Edge-AI applications still face considerable challenges in enhancing computational efficiency in resource-constrained environments. This work presents RAMAN, a resource-efficient and approximate posit(8,2)-based Multiply-Accumulate (MAC) architecture designed to improve hardware efficiency within bandwidth limitations. The proposed REAP (Resource-Efficient Approximate Posit) MAC engine, which is at the core of RAMAN, uses approximation in the posit multiplier to achieve significant area and power reductions with an impact on accuracy. To support diverse AI workloads, this MAC unit is incorporated in a scalable Vector Execution Unit (VEU), which permits hardware reuse and parallelism among deep neural network layers. Furthermore, we propose an algorithm-hardware co-design framework incorporating approximation-aware training to evaluate the impact of hardware-level approximation on application-level performance. Empirical validation on FPGA and ASIC platforms shows that the proposed REAP MAC achieves up to 46% in LUT savings and 35.66% area, 31.28% power reduction, respectively, over the baseline Posit Dot-Product Unit (PDPU) design, while maintaining high accuracy (98.45%) for handwritten digit recognition. RAMAN demonstrates a promising trade-off between hardware efficiency and learning performance, making it suitable for next-generation edge intelligence.

RAMAN: Resource-efficient ApproxiMate Posit Processing for Algorithm-Hardware Co-desigN

TL;DR

RAMAN tackles the challenge of resource-constrained edge AI by introducing a resource-efficient approximate MAC (REAP) and a scalable Vector Execution Unit. Through an algorithm-hardware co-design framework with approximation-aware training, RAMAN balances hardware efficiency with application accuracy, demonstrated on FPGA and ASIC with substantial resource savings and strong MNIST accuracy. Key contributions include the REAP MAC, a modular VEU that enables reuse across diverse workloads, and a quantization-aware training workflow validated via Tiny-YOLOv3. This work offers a practical path toward high-density, energy-efficient edge accelerators that maintain robust learning performance under hardware approximation.

Abstract

Edge-AI applications still face considerable challenges in enhancing computational efficiency in resource-constrained environments. This work presents RAMAN, a resource-efficient and approximate posit(8,2)-based Multiply-Accumulate (MAC) architecture designed to improve hardware efficiency within bandwidth limitations. The proposed REAP (Resource-Efficient Approximate Posit) MAC engine, which is at the core of RAMAN, uses approximation in the posit multiplier to achieve significant area and power reductions with an impact on accuracy. To support diverse AI workloads, this MAC unit is incorporated in a scalable Vector Execution Unit (VEU), which permits hardware reuse and parallelism among deep neural network layers. Furthermore, we propose an algorithm-hardware co-design framework incorporating approximation-aware training to evaluate the impact of hardware-level approximation on application-level performance. Empirical validation on FPGA and ASIC platforms shows that the proposed REAP MAC achieves up to 46% in LUT savings and 35.66% area, 31.28% power reduction, respectively, over the baseline Posit Dot-Product Unit (PDPU) design, while maintaining high accuracy (98.45%) for handwritten digit recognition. RAMAN demonstrates a promising trade-off between hardware efficiency and learning performance, making it suitable for next-generation edge intelligence.
Paper Structure (7 sections, 9 equations, 7 figures, 2 tables)

This paper contains 7 sections, 9 equations, 7 figures, 2 tables.

Table of Contents

  1. Introduction
  2. Proposed Work
  3. Resource-Efficient Approximate $\mathrm{posit}(8,2)$ MAC
  4. Vector Execution Unit
  5. Algorithm-Hardware co-design
  6. Performance Evaluation
  7. Conclusion & Future Work

Figures (7)

  • Figure 1: Workload characterization demonstrating implications of Resource-efficient MAC computations for different AI workloadsFlex-PE.
  • Figure 2: Data multiplexed and hardware reused AI accelerator (HYDRA) architecture with primary emphasis on MAC units, adapted from GR-Neuro.
  • Figure 3: Detailed data-path for the proposed resource-efficient approximate Posit MAC unit.
  • Figure 4: Detailed AI accelerator architecture, showing Vector Execution Unit (VEU)
  • Figure 5: Detailed methodology/workflow describing Algorithm--Hardware co-design utilized in the empirical evaluation of approximate posit processing.
  • ...and 2 more figures