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Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis

Eashan Wadhwa, Shanker Shreejith

TL;DR

Dynamic power in FPGAs is driven by switching activity and scales with $P_{dyn} \approx \alpha C V^2 f$. Simopt-Power leverages per-signal toggle metadata from simulation to drive a Shannon-decomposition based truth-table splitting and logic duplication during synthesis-mapping, aiming to reduce output capacitance and switching events without altering functionality. Evaluations on RTTLM and Koios benchmarks show measurable power reductions (roughly 5–9% on average) with area overheads around 18–19% LUT-equivalents, illustrating a practical path to power-aware FPGA design using simulation metadata. Future work targets refined cost models, open-source power estimation, and extension to heterogeneous fabrics and run-time reconfiguration for higher dynamic-power savings.

Abstract

Excessive switching activity is a primary contributor to dynamic power dissipation in modern FPGAs, where fine-grained configurability amplifies signal toggling and associated capacitance. Conventional low-power techniques -- gating, clock-domain partitioning, and placement-aware netlist rewrites - either require intrusive design changes or offer diminishing returns as device densities grow. In this work, we present Simopt-power, a simulator-driven optimisation framework that leverages simulation analysis to identify and selectively reconfigure high-toggle paths. By feeding activity profiles back into a lightweight transformation pass, Simopt-power judiciously inserts duplicate truth table logic using Shannon Decomposition principle and relocates critical nets, thereby attenuating unnecessary transitions without perturbing functional behaviour. We evaluated this framework on open-source RTLLM benchmark, with Simopt-power achieves an average switching-induced power reduction of ~9\% while incurring only ~9\% additional LUT-equivalent resources for arithmetic designs. These results demonstrate that coupling simulation insights with targeted optimisations can yield a reduced dynamic power, offering a practical path toward using simulation metadata in the FPGA-CAD flow.

Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis

TL;DR

Dynamic power in FPGAs is driven by switching activity and scales with . Simopt-Power leverages per-signal toggle metadata from simulation to drive a Shannon-decomposition based truth-table splitting and logic duplication during synthesis-mapping, aiming to reduce output capacitance and switching events without altering functionality. Evaluations on RTTLM and Koios benchmarks show measurable power reductions (roughly 5–9% on average) with area overheads around 18–19% LUT-equivalents, illustrating a practical path to power-aware FPGA design using simulation metadata. Future work targets refined cost models, open-source power estimation, and extension to heterogeneous fabrics and run-time reconfiguration for higher dynamic-power savings.

Abstract

Excessive switching activity is a primary contributor to dynamic power dissipation in modern FPGAs, where fine-grained configurability amplifies signal toggling and associated capacitance. Conventional low-power techniques -- gating, clock-domain partitioning, and placement-aware netlist rewrites - either require intrusive design changes or offer diminishing returns as device densities grow. In this work, we present Simopt-power, a simulator-driven optimisation framework that leverages simulation analysis to identify and selectively reconfigure high-toggle paths. By feeding activity profiles back into a lightweight transformation pass, Simopt-power judiciously inserts duplicate truth table logic using Shannon Decomposition principle and relocates critical nets, thereby attenuating unnecessary transitions without perturbing functional behaviour. We evaluated this framework on open-source RTLLM benchmark, with Simopt-power achieves an average switching-induced power reduction of ~9\% while incurring only ~9\% additional LUT-equivalent resources for arithmetic designs. These results demonstrate that coupling simulation insights with targeted optimisations can yield a reduced dynamic power, offering a practical path toward using simulation metadata in the FPGA-CAD flow.
Paper Structure (8 sections, 2 equations, 3 figures, 2 tables, 2 algorithms)

This paper contains 8 sections, 2 equations, 3 figures, 2 tables, 2 algorithms.

Table of Contents

  1. Introduction
  2. Preliminaries
  3. Verilog-To-Routing and Simulators
  4. FPGA netlist to placed design
  5. Simulation in Simopt
  6. Simopt-power
  7. Results
  8. Conclusion and Future work

Figures (3)

  • Figure 1: A standard Yosys synthesis flow, where HDL is synthesised to a gate-level netlist, followed by the generation of a BLIF logic netlist.
  • Figure 2: How Simopt-Power integrates into the Simopt framework. The red box indicates the step where the proposed truth-table decomposition step is integrated.
  • Figure 3: Simopt-power truth-table decomposed synthesis netlist of the counter from Fig.\ref{['fig:synthesisflow']}(b). The grey box indicates the additional LUT logic added by the Simopt-Power framework to reduce power.