Real-time decoding of the gross code memory with FPGAs

TL;DR

This work presents an FPGA realization of the Relay-BP decoder for quantum LDPC bicycle codes, achieving real-time, low-latency decoding essential for fault-tolerant quantum computing. Building on DMem-BP, the Relay-BP architecture uses memory-strength based belief propagation and a relay ensemble to improve convergence and accuracy, implemented on dedicated compute units wired directly to the decoding graph to maximize throughput. The hardware demonstrates high performance on memory experiments with the Loon and gross codes, attaining a per-iteration time of $24\, \\mathrm{ns}$ and supporting windowed decoding that can process 12-cycle syndrome windows within sub-microsecond budgets under favorable noise models; reduced-precision integer arithmetic preserves logical accuracy while dramatically reducing gateware area. Verification with a real-time controller and synthetic syndrome data confirms correct data flow, convergence behavior, and compatibility with future integration into QPU control systems. The results illuminate a practical path toward scalable, real-time QEC decoders for superconducting qubits and large quantum LDPC codes, highlighting both the potential and the remaining engineering challenges for hardware-accelerated fault-tolerance.

Abstract

We introduce a prototype FPGA decoder implementing the recently discovered Relay-BP algorithm and targeting memory experiments on the $[[144,12,12]]$ bivariate bicycle quantum low-density parity check code. The decoder is both fast and accurate, achieving a belief propagation iteration time of 24ns. It matches the logical error performance of a floating-point implementation despite using reduced precision arithmetic. This speed is sufficient for an average per cycle decoding time under $1\,\mathrm{μs}$ assuming circuit model error probabilities are less than $3 \times 10^{-3}$. This prototype decoder offers useful insights on the path toward decoding solutions for scalable fault-tolerant quantum computers.

Figures (8)

• Figure 1: The decoding graph visually represents the check matrix: circular ($\ocircle$) error nodes correspond to columns of $\mathbf{H}$, and square ($\square$) check nodes to its rows. Filled or unfilled nodes denote a corresponding value of 1 or 0 in either $\bm{\sigma}$ or $\mathbf{e}$. The decoder relies solely on the syndrome (i.e., the values of the check nodes) to infer a candidate error. Check node $i$ has syndrome $\sigma_i = 1$ if it touches an odd number of error nodes with value one.
• Figure 2: Overview of the Relay-BP FPGA decoder architecture. An external nest handles configuration control and includes adapters to conform the I/O data streams to the requirements of the decoder. The windowing decoder creates a window of detectors from the input data stream of syndromes and converts the output error vector $\mathbf{\hat{e}}$ into an update to the logical Pauli frame via the logical action matrix $\mathbf{A}$. The central Relay decoder handles execution of the Relay-BP algorithm via a collection of specialized compute nodes the correspond 1:1 with the decoding graph $G$. The connectivity of $G$ is translated into FPGA wiring defining the mapping of messages between the compute nodes.
• Figure 3: a) Schematic of the check node unit (CNU). We note that the exclusive minimum is not fully calculated in the CNU. Instead only the minimum and second minimum are calculated in the CNU with the exclusive minimum being calculated in the VNU at a later time. b) Schematic of the variable node unit (VNU). c) Schematic of the Relay adder that is used in the VNUs.
• Figure 4: Contour plots along the range of maximum-iteration counts for BP and DMem-BP or maximum-leg counts $R$ for Relay of logical error rate vs average BP iteration count for decoding Z syndromes of a 12 syndrome cycle and a final noiseless cycle of the gross code. We show results from standard BP as well as DMem-BP ($\gamma_0=0.1$) and Relay-S ($\gamma_0=0.1$, $\gamma\in[-0.24,0.66]$, $\beta_\textrm{int}\in[3,10]$, $T_0=T_r=60$), for a software implementation of Belief Propagation in float-64, as well as software emulation of the FPGA logic at int4.2.8 precision. For Relay-BP, we observe an improvement in the average number of iterations to converge for the integer implementation at a small cost to logical error rate.
• Figure 5: (Left) Floorplan of a 12-cycle gross code CSS decoder for X in an AMD XCVU19P FPGA. Colors reflects logic instantiated due to entries of the decoding matrix local to a unique syndrome cycle within the 12-cycle wide decoding matrix. (Right) Resource utilization table after synthesis and place and route. The decoder has it's own independent clock domain, so we report it's cycle times separately.