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Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs

Misaki Kida, Shimpei Sato

TL;DR

The paper addresses the need for area- and latency-efficient low-bitwidth multipliers suitable for dense FPGA-based edge inference. It proposes a hand-optimized exact 4-bit multiplier for Xilinx 7-series FPGAs that uses only 11 LUTs and 2 CARRY4 blocks by carefully mapping 3 LUT6_2 and 8 LUT6 elements to generate the sixteen partial products and accumulate them, and by algebraically simplifying carry logic with $C1 = A1B2 \cdot A2B1$. The design achieves a critical-path delay of $2.750~\text{ns}$ while preserving exact accuracy, outperforming several prior 4-bit multiplier baselines in resource usage and approaching the best delay among exact designs. Validation includes exhaustive functional verification and post-place-and-route CPD measurements on an Artix-7 35T, demonstrating strong potential for high-density, low-latency LUT-based accelerators in edge workloads.

Abstract

As IoT and edge inference proliferate,there is a growing need to simultaneously optimize area and delay in lookup-table (LUT)-based multipliers that implement large numbers of low-bitwidth operations in parallel. This paper proposes a hardwareefficientaccurate 4-bit multiplier design for AMD Xilinx 7-series FPGAs using only 11 LUTs and two CARRY4 blocks. By reorganizing the logic functions mapped to the LUTs, the proposed method reduces the LUT count by one compared with the prior 12-LUT design while also shortening the critical path. Evaluation confirms that the circuit attains minimal resource usage and a critical-path delay of 2.750 ns.

Hardware-Efficient Accurate 4-bit Multiplier for Xilinx 7 Series FPGAs

TL;DR

The paper addresses the need for area- and latency-efficient low-bitwidth multipliers suitable for dense FPGA-based edge inference. It proposes a hand-optimized exact 4-bit multiplier for Xilinx 7-series FPGAs that uses only 11 LUTs and 2 CARRY4 blocks by carefully mapping 3 LUT6_2 and 8 LUT6 elements to generate the sixteen partial products and accumulate them, and by algebraically simplifying carry logic with . The design achieves a critical-path delay of while preserving exact accuracy, outperforming several prior 4-bit multiplier baselines in resource usage and approaching the best delay among exact designs. Validation includes exhaustive functional verification and post-place-and-route CPD measurements on an Artix-7 35T, demonstrating strong potential for high-density, low-latency LUT-based accelerators in edge workloads.

Abstract

As IoT and edge inference proliferate,there is a growing need to simultaneously optimize area and delay in lookup-table (LUT)-based multipliers that implement large numbers of low-bitwidth operations in parallel. This paper proposes a hardwareefficientaccurate 4-bit multiplier design for AMD Xilinx 7-series FPGAs using only 11 LUTs and two CARRY4 blocks. By reorganizing the logic functions mapped to the LUTs, the proposed method reduces the LUT count by one compared with the prior 12-LUT design while also shortening the critical path. Evaluation confirms that the circuit attains minimal resource usage and a critical-path delay of 2.750 ns.
Paper Structure (6 sections, 5 figures, 3 tables)

This paper contains 6 sections, 5 figures, 3 tables.

Table of Contents

  1. Introduction
  2. Preliminary
  3. Related Works
  4. Proposed Design
  5. Experimental Results
  6. Conclusion

Figures (5)

  • Figure 1: Configuration of LUT6 and LUT6_2. Xilinx LUTs can be configured to operate as either a 6-input 1-output or a 5-input 2-output device by setting the MUX behavior.
  • Figure 2: CARRY4 configuration. The result of adding the values input via DI and S, including the carry, is output to O.
  • Figure 3: Partial Product Accumulation for 4-bit multiply
  • Figure 4: Block diagram of proposed accurate 4-bit multiplier.
  • Figure 5: Performance comparison of 4-bit multipliers.