FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs

TL;DR

FIFOAdvisor, a framework that automatically determines FIFO sizes in HLS designs and delivers significant runtime speedups over traditional HLS/RTL co-simulation, is presented and revealed Pareto-optimal latency-memory frontiers across optimization strategies.

Abstract

Dataflow hardware designs enable efficient FPGA implementations via high-level synthesis (HLS), but correctly sizing first-in-first-out (FIFO) channel buffers remains challenging. FIFO sizes are user-defined and balance latency and area-undersized FIFOs cause stalls and potential deadlocks, while oversized ones waste memory. Determining optimal sizes is non-trivial: existing methods rely on restrictive assumptions, conservative over-allocation, or slow RTL simulations. We emphasize that runtime-based analyses (i.e., simulation) are the only reliable way to ensure deadlock-free FIFO optimization for data-dependent designs. We present FIFOAdvisor, a framework that automatically determines FIFO sizes in HLS designs. It leverages LightningSim, a 99.9\% cycle-accurate simulator supporting millisecond-scale incremental runs with new FIFO configurations. FIFO sizing is formulated as a dual-objective black-box optimization problem, and we explore heuristic and search-based methods to characterize the latency-resource trade-off. FIFOAdvisor also integrates with Stream-HLS, a framework for optimizing affine dataflow designs lowered from C++, MLIR, or PyTorch, enabling deeper optimization of FIFOs in these workloads. We evaluate FIFOAdvisor on Stream-HLS design benchmarks spanning linear algebra and deep learning workloads. Our results reveal Pareto-optimal latency-memory frontiers across optimization strategies. Compared to baseline designs, FIFOAdvisor achieves much lower memory usage with minimal delay overhead. Additionally, it delivers significant runtime speedups over traditional HLS/RTL co-simulation, making it practical for rapid design space exploration. We further demonstrate its capability on a complex accelerator with data-dependent control flow. Code and results: https://github.com/sharc-lab/fifo-advisor

Figures (6)

• Figure 1: Overview of FIFOAdvisor, highlighting the limitations of previous FIFO sizing techniques and the advantages of our multi-objective optimization approach using LightningSim for fast, cycle-accurate simulation. FIFOAdvisor generates a Pareto frontier of candidate solutions that trade off between memory usage reduction and latency overhead.
• Figure 2: HLS designs with FIFOs that can not be sized optimally or in a deadlock-free manner without runtime analysis (e.g. simulation)
• Figure 3: Pareto frontiers for the selected k15mmtree, k15mmtseq, and Autoencoder designs. The "highlighted Pareto points" ($\bigstar$, using $\alpha = 0.7$) are used for comparison against the Baseline-Min (✖) and Baseline-Max points (✖) as described in §\ref{['sec:pareto']}.
• Figure 4: FIFO memory usage and relative latency of "highlighted Pareto points" ($\bigstar$) relative to the naïvely-sized baseline designs (✖ and ✖). Each bar represents a single design. For all metrics, lower is better. The down arrow black$\downarrow$ indicates no BRAMs were used for all FIFOs in a given design. ✕black$\rightarrow$✓ indicates that a Baseline-Min design was un-deadlocked by FIFOAdvisor.
• Figure 5: Iso-runtime comparison of different optimizers on the k15mmtree design. Runtime includes optimizer logic overhead and calls to LightningSim to evaluate new FIFO configurations.