Magnetic tunnel junction as a real-time entropy source: Field-Programmable Gate Array based random bit generation without post-processing

TL;DR

The paper addresses the need for fast, truly random bits without post-processing. It develops a real-time feedback loop that stabilizes MTJ switching probability and an on-board FPGA XOR to suppress short-term correlations, delivering NIST-compliant randomness at 5 Mb/s. Experimental results show that only the combination of feedback and XOR yields a stream that passes the NIST tests across durations, with significantly reduced drift and correlations. This work provides a practical hardware TRNG based on magnetic tunnel junctions, with immediate applications in cryptography, stochastic computing, and large-scale simulations, and outlines routes to higher throughput and FPGA-implemented randomness checks.

Abstract

We demonstrate a method to generate application-ready truly random bits from a magnetic tunnel junction driven by a Field-Programmable Gate Array (FPGA). We implement a real-time feedback loop that stabilizes the switching probability near 50\% and apply an XOR operation, both on the FPGA, to suppress short-term correlations, together mitigating long-term drift and bias in the bitstream. This combined approach enables NIST-compliant random bit generation at 5~Mb/s without post-processing, providing a practical hardware solution for fast and reliable true random number generation. Beyond cryptographic applications, these capabilities open opportunities for stochastic hardware accelerators, probabilistic computing, and large-scale modeling where real-time access to unbiased randomness is essential.

Figures (6)

• Figure 1: Our custom-designed circuit uses an FPGA to control a sequence of voltage pulses that are repeatedly applied to the magnetic tunnel junction (MTJ). A transimpedance amplifier converts the small difference in current between pMTJ states into a two-level voltage signal that the FPGA registers as a stream of 0s and 1s Dubovskiy2024. A major improvement in this design is the inclusion of a real-time debiasing feedback loop, which continuously averages the bitstream over a defined time window and sends an Inter-Integrated Circuit (I²C) signal to the DAC to dynamically adjust the write-pulse voltage. In addition, an XOR operation is performed on the FPGA to de-correlate bits before the processed stream is transmitted to the host computer via Ethernet.
• Figure 2: The pulse sequence shown in the upper left inset is applied to the junction at a repetition rate of approximately 10.6 MHz to generate random bits. A large reset (R) pulse initializes the junction to a known state, which is verified by a smaller verify (V) pulse. A stochastic write (W) pulse of opposite polarity produces a random MTJ state, followed by a measure (M) pulse---identical to the verify pulse---that reads the final state. The FPGA is used to systematically increase the write-pulse amplitude in steps of 0.44 mV and the switching probability is plotted as a function of write voltage with 10 million trials per step. The voltage at which the probability of switching is 50% is denoted as $V_{1/2}$; the x axis shows the deviation from this voltage.
• Figure 3: The FPGA controls voltages on eight DAC channels, four of which are used in the pulse sequence, each gated by an analog switch. Four of the eight channels are first inverted to negative voltages before being switched, and one of these is used for the writing pulse. During the measure (M) pulse, the current through the MTJ is amplified by a transimpedance amplifier, compared to a threshold, and recorded by the FPGA as a single bit. The results from repeated trials are averaged over time, and a feedback signal adjusts the write-pulse amplitude to maintain a switching probability near 50%.
• Figure 4: Four trials varying the usage of feedback and XOR. Each trial has a total of $10^{11}$ bits, collected at a rate of 10.6 Mb/s. The results were averaged in bins of $10^5$ bits, and their index was converted to time on the x axis. The change in write pulse, $\Delta{V} = V_W - V_{1/2}$ is plotted simultaneously in the upper panel of each figure. a) No feedback no XOR: we observed large drifts in probability and large short timescale variation. b) Feedback no XOR: the long term drifts were eliminated, but the large variation remained. The write voltage increased slightly during the experiment c) No feedback XOR: Now collected at an effective rate of 5.3 MHz, the short term variation was greatly reduced, but the drift was still present. d) Feedback XOR: Both the drift and variation have been significantly reduced. Again, the write voltage increased over the course of the experiment.
• Figure 5: A sample of the first billion bits from each data set are averaged in bins of $N = 10^5$ bits and placed in bins $4\times10^{-3}$ percent wide. The results are compared to the expected binomial function described in Eq. \ref{['binomial']}. Here $50$ % is the target probability and $x\in [0,100]$. We observed that the dataset with both XOR and feedback best fits the expected distribution.